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| author | Andrew Trick <atrick@apple.com> | 2013-09-04 23:54:00 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-09-04 23:54:00 +0000 |
| commit | d4486ebd5f9b727fc73407b93a7d83aab7551179 (patch) | |
| tree | 34757df64bf782226b42e0178e135b7d26d5c229 /test/CodeGen | |
| parent | a38c27be0ff5dd35fcd20cfce827f9dbdb24d1ea (diff) | |
| download | llvm-d4486ebd5f9b727fc73407b93a7d83aab7551179.tar.gz llvm-d4486ebd5f9b727fc73407b93a7d83aab7551179.tar.bz2 llvm-d4486ebd5f9b727fc73407b93a7d83aab7551179.tar.xz | |
mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190014 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/misched-copy.ll | 18 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-matmul.ll | 9 |
2 files changed, 11 insertions, 16 deletions
diff --git a/test/CodeGen/X86/misched-copy.ll b/test/CodeGen/X86/misched-copy.ll index 5970dcd31f..4485b8a244 100644 --- a/test/CodeGen/X86/misched-copy.ll +++ b/test/CodeGen/X86/misched-copy.ll @@ -1,12 +1,4 @@ ; REQUIRES: asserts -; -; FIXME: The following line is a hack to remove any stray files which might have -; been left dangling around by this test. It can be removed once the various -; bots have cycled past this commit. -; -; RUN: rm -f misched-copy.s %S/misched-copy.s -; -; ; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s ; ; Test scheduling of copy instructions. @@ -16,11 +8,11 @@ ; MUL_HiLo PhysReg use copies should be just above the mul. ; MUL_HiLo PhysReg def copies should be just below the mul. ; -; CHECK: *** Final schedule for BB#1 *** -; CHECK-NEXT: %EAX<def> = COPY -; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; -; CHECK-NEXT: COPY %E{{[AD]}}X; -; CHECK-NEXT: COPY %E{{[AD]}}X; +; CHECK: *** Final schedule for BB#1 *** +; CHECK: %EAX<def> = COPY +; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; +; CHECK-NEXT: COPY %E{{[AD]}}X +; CHECK-NEXT: COPY %E{{[AD]}}X ; CHECK: DIVSSrm define i64 @mulhoist(i32 %a, i32 %b) #0 { entry: diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll index fe78e70f05..5454b7cf78 100644 --- a/test/CodeGen/X86/misched-matmul.ll +++ b/test/CodeGen/X86/misched-matmul.ll @@ -3,11 +3,14 @@ ; ; Verify that register pressure heuristics are working in MachineScheduler. ; -; When we enable subtree scheduling heuristics on X86, we may need a -; flag to disable it for this test case. +; We can further reduce spills in this case with a global register +; pressure heuristic, like sethi-ullman numbers or biasing toward +; scheduled subtrees. However, these heuristics are marginally +; beneficial on x86_64 and exacerbate register pressure in other +; more complex cases. ; ; CHECK: @wrap_mul4 -; CHECK: 22 regalloc - Number of spills inserted +; CHECK: 23 regalloc - Number of spills inserted define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 { entry: |