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| author | Tim Northover <tnorthover@apple.com> | 2013-10-22 19:00:39 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-22 19:00:39 +0000 |
| commit | 01b0e94bb731310e72f66977e4b57cd3f3280ba4 (patch) | |
| tree | 71431ebc46e5dacada269ca9c27a0350d13ab6f8 /test/MC/Disassembler/ARM | |
| parent | e18273b7be11878999a2ee199d0b1ec468474c9c (diff) | |
| download | llvm-01b0e94bb731310e72f66977e4b57cd3f3280ba4.tar.gz llvm-01b0e94bb731310e72f66977e4b57cd3f3280ba4.tar.bz2 llvm-01b0e94bb731310e72f66977e4b57cd3f3280ba4.tar.xz | |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/ARM')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-thumbv7.txt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt index 16970844ae..2c84b8a7aa 100644 --- a/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -389,3 +389,19 @@ [0x80 0xf9 0x30 0x0b] # CHECK: invalid instruction encoding # CHECK-NEXT: [0x80 0xf9 0x30 0x0b] + + +#------------------------------------------------------------------------------ +# Unpredictable STMs +#------------------------------------------------------------------------------ + +# 32-bit Thumb STM instructions cannot have a writeback register which appears +# in the list. + +[0xa1,0xe8,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] + +[0x21,0xe9,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0x21,0xe9,0x07,0x04] |