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| author | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-24 09:15:01 +0000 |
|---|---|---|
| committer | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-24 09:15:01 +0000 |
| commit | ebc3938ae717d7352de800344c3ad5a1bceb74e5 (patch) | |
| tree | 67c7db18cabf43a3191c20fdc60e24e97ea5369a /test/MC/Disassembler/ARM | |
| parent | 07c3e159d8fffc8b16bcd52cc395a78007c62910 (diff) | |
| download | llvm-ebc3938ae717d7352de800344c3ad5a1bceb74e5.tar.gz llvm-ebc3938ae717d7352de800344c3ad5a1bceb74e5.tar.bz2 llvm-ebc3938ae717d7352de800344c3ad5a1bceb74e5.tar.xz | |
ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/ARM')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-NEON-thumb.txt | 9 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VFP-thumb.txt | 9 |
2 files changed, 18 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt new file mode 100644 index 0000000000..a191d9e118 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt @@ -0,0 +1,9 @@ +# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) + +# VMOV +# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VDUP +# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt new file mode 100644 index 0000000000..7a4ddaa0a4 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt @@ -0,0 +1,9 @@ +# VFP instructions with invalid predicate bits (pred != 0b1110) + +# VABS +# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VMLA +# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding |