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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-04-30 09:00:12 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-04-30 09:00:12 +0000 |
| commit | 62d77858be88ca011b55f5b350152bf04d1ca7db (patch) | |
| tree | 96f11b2a558e60b360dddf66ebb438553a2f6ec3 /test/MC/Disassembler | |
| parent | defce4cfd607e013169033164def7a3e558bfd54 (diff) | |
| download | llvm-62d77858be88ca011b55f5b350152bf04d1ca7db.tar.gz llvm-62d77858be88ca011b55f5b350152bf04d1ca7db.tar.bz2 llvm-62d77858be88ca011b55f5b350152bf04d1ca7db.tar.xz | |
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index 0cff28ad2b..ecab5a5758 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. 0xde 0x69 0x18 0x46 |