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| author | Tim Northover <tnorthover@apple.com> | 2013-09-13 07:26:52 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-09-13 07:26:52 +0000 |
| commit | 630c5e06d633fad142af4b145ee684e90754700e (patch) | |
| tree | c3cbf46f05c9144cd434f687ca36d9247529d7b7 /test/MC/Disassembler | |
| parent | dc6fc4fa1f88e4accf1abe6db67399496bfe18b2 (diff) | |
| download | llvm-630c5e06d633fad142af4b145ee684e90754700e.tar.gz llvm-630c5e06d633fad142af4b145ee684e90754700e.tar.bz2 llvm-630c5e06d633fad142af4b145ee684e90754700e.tar.xz | |
AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.
The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
| -rw-r--r-- | test/MC/Disassembler/AArch64/neon-instructions.txt | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index fa9f73fe2a..ecb6249faf 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -131,8 +131,11 @@ #------------------------------------------------------------------------------ # Vector Move - register #------------------------------------------------------------------------------ -# CHECK: mov v1.16b, v15.16b -# CHECK: mov v25.8b, v4.8b + +# FIXME: these should print as "mov", but TableGen can't handle it. + +# CHECK: orr v1.16b, v15.16b, v15.16b +# CHECK: orr v25.8b, v4.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e |