diff options
| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-18 09:28:35 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-18 09:28:35 +0000 |
| commit | 764f6f51257a0669acc58c8e5b4b802a29069302 (patch) | |
| tree | 7026cb542a05eb50fb9df96f3f6ec2630178313d /test/MC/Mips/mips-fpu-instructions.s | |
| parent | fe754512dcab6bb4bce4d3ea370c3202894e711b (diff) | |
| download | llvm-764f6f51257a0669acc58c8e5b4b802a29069302.tar.gz llvm-764f6f51257a0669acc58c8e5b4b802a29069302.tar.bz2 llvm-764f6f51257a0669acc58c8e5b4b802a29069302.tar.xz | |
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/mips-fpu-instructions.s')
| -rw-r--r-- | test/MC/Mips/mips-fpu-instructions.s | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index e515872f26..5ff31f3e49 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -158,6 +158,8 @@ # CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] # CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] +# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c] +# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -179,3 +181,5 @@ mtc2 $9, $4, 5 movf $2, $1, $fcc0 movt $2, $1, $fcc0 + luxc1 $f0, $a2($a1) + suxc1 $f4, $t8($a1)
\ No newline at end of file |