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| author | Jack Carter <jcarter@mips.com> | 2012-10-06 01:17:37 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-10-06 01:17:37 +0000 |
| commit | de3322746280b957d552cc5e69e121b38c07406c (patch) | |
| tree | 06eb6222f97628ce447b7e1d23b2c845b7df1776 /test/MC/Mips | |
| parent | 2490dc650895149423bb59538dc03ca352222702 (diff) | |
| download | llvm-de3322746280b957d552cc5e69e121b38c07406c.tar.gz llvm-de3322746280b957d552cc5e69e121b38c07406c.tar.bz2 llvm-de3322746280b957d552cc5e69e121b38c07406c.tar.xz | |
Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips')
| -rw-r--r-- | test/MC/Mips/mips-fpu-instructions.s | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index ce8024d45b..a126c6f718 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -149,6 +149,14 @@ # CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00] # CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00] # CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4] +# CHECK: mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40] +# CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40] +# CHECK: mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48] +# CHECK: mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48] +# CHECK: mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40] +# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] +# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] +# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -160,3 +168,11 @@ mthi $a3 mtlo $a3 swc1 $f9,9158($a3) + mfc0 $6, $7 + mtc0 $9, $8 + mfc2 $5, $7 + mtc2 $9, $4 + mfc0 $6, $7, 2 + mtc0 $9, $8, 3 + mfc2 $5, $7, 4 + mtc2 $9, $4, 5 |