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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 23:33:29 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 23:33:29 +0000 |
| commit | 228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b (patch) | |
| tree | 495ce8f8ca372d6efb3347018fd8803b015ff810 /test/MC/PowerPC | |
| parent | 74d2a3e1a014b93e9037a7b04e85dc92bfb54fa7 (diff) | |
| download | llvm-228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b.tar.gz llvm-228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b.tar.bz2 llvm-228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b.tar.xz | |
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
| -rw-r--r-- | test/MC/PowerPC/ppc64-fixups.s | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index 18811fa411..612c899b06 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -25,8 +25,6 @@ beqa target -# FIXME: .TOC.@tocbase - # CHECK: li 3, target@l # encoding: [0x38,0x60,A,A] # CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 @@ -393,3 +391,22 @@ base: # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16 target 0x0 addi 3, 3, target@got@tlsld + +# Data relocs +# llvm-mc does not show any "encoding" string for data, so we just check the relocs + +# CHECK-REL: .rela.data + .data + +# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TOC - 0x0 + .quad .TOC.@tocbase + +# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPMOD64 target 0x0 + .quad target@dtpmod + +# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TPREL64 target 0x0 + .quad target@tprel + +# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPREL64 target 0x0 + .quad target@dtprel + |