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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-05 12:22:36 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-05 12:22:36 +0000 |
| commit | 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df (patch) | |
| tree | 93954d1ea2e8230d74fceb259dbc4566b6ea8901 /test/MC/PowerPC | |
| parent | 87b8a7f9996ee7463b787fc85394287de903c7d7 (diff) | |
| download | llvm-23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df.tar.gz llvm-23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df.tar.bz2 llvm-23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df.tar.xz | |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
| -rw-r--r-- | test/MC/PowerPC/ppc64-errors.s | 10 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-fixups.s | 7 |
2 files changed, 15 insertions, 2 deletions
diff --git a/test/MC/PowerPC/ppc64-errors.s b/test/MC/PowerPC/ppc64-errors.s index 8b6dd5395f..bc8c95c223 100644 --- a/test/MC/PowerPC/ppc64-errors.s +++ b/test/MC/PowerPC/ppc64-errors.s @@ -12,6 +12,16 @@ # CHECK-NEXT: add %r32, %r32, %r32 add %r32, %r32, %r32 +# TLS register operands + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: add 3, symbol@tls, 4 + add 3, symbol@tls, 4 + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: subf 3, 4, symbol@tls + subf 3, 4, symbol@tls + # Signed 16-bit immediate operands # CHECK: error: invalid operand for instruction diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index 937e55758e..9f23882e45 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -206,8 +206,6 @@ base: # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0 ld 1, target@got@l(3) -# FIXME: @tls - # CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] # CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16 @@ -405,6 +403,11 @@ base: # CHECK-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 bl __tls_get_addr(target@tlsld) +# CHECK: add 3, 4, target@tls # encoding: [0x7c,0x64,0x6a,0x14] +# CHECK-NEXT: # fixup A - offset: 0, value: target@tls, kind: fixup_ppc_nofixup +# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLS target 0x0 + add 3, 4, target@tls + # Data relocs # llvm-mc does not show any "encoding" string for data, so we just check the relocs |