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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-06-25 13:17:10 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-06-25 13:17:10 +0000
commit816c06f7fa73e8150e260a11d897be2f52d4f2b8 (patch)
tree28e891aec79605d5ab948d3230f323b6d52c5d94 /test/MC/PowerPC
parent9c52f81e1787dc9666e510f5b7a0ea75b697cd0b (diff)
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[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction from the rotate/shift family that were missing). They are currently used only by the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
-rw-r--r--test/MC/PowerPC/ppc64-encoding.s12
1 files changed, 8 insertions, 4 deletions
diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s
index 377000f1d2..edf18eb96a 100644
--- a/test/MC/PowerPC/ppc64-encoding.s
+++ b/test/MC/PowerPC/ppc64-encoding.s
@@ -444,14 +444,18 @@
rldicr 2, 3, 4, 5
# CHECK: rldicr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x45]
rldicr. 2, 3, 4, 5
-# FIXME: rldic 2, 3, 4, 5
-# FIXME: rldic. 2, 3, 4, 5
+# CHECK: rldic 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x48]
+ rldic 2, 3, 4, 5
+# CHECK: rldic. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x49]
+ rldic. 2, 3, 4, 5
# CHECK: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50]
rldcl 2, 3, 4, 5
# CHECK: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51]
rldcl. 2, 3, 4, 5
-# FIXME: rldcr 2, 3, 4, 5
-# FIXME: rldcr. 2, 3, 4, 5
+# CHECK: rldcr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x52]
+ rldcr 2, 3, 4, 5
+# CHECK: rldcr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x53]
+ rldcr. 2, 3, 4, 5
# CHECK: rldimi 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4c]
rldimi 2, 3, 4, 5
# CHECK: rldimi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4d]