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| author | Chad Rosier <mcrosier@apple.com> | 2013-05-10 18:24:17 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-05-10 18:24:17 +0000 |
| commit | ffc49cbea41c08132587a3e622bb65191fa576a2 (patch) | |
| tree | cf479f40217f1d261715eef987c2a100f004f055 /test/MC/X86 | |
| parent | 6e53180db120b30f600ac31611a9dd47ef7f4921 (diff) | |
| download | llvm-ffc49cbea41c08132587a3e622bb65191fa576a2.tar.gz llvm-ffc49cbea41c08132587a3e622bb65191fa576a2.tar.bz2 llvm-ffc49cbea41c08132587a3e622bb65191fa576a2.tar.xz | |
[ms-inline asm] Fix a crasher when we fail on a direct match.
The issue was that the MatchingInlineAsm and VariantID args to the
MatchInstructionImpl function weren't being set properly. Specifically, when
parsing intel syntax, the parser thought it was parsing inline assembly in the
at&t dialect; that will never be the case.
The crash was caused when the emitter tried to emit the instruction, but the
operands weren't set. When parsing inline assembly we only set the opcode, not
the operands, which is used to lookup the instruction descriptor.
rdar://13854391 and PR15945
Also, this commit reverts r176036. Now that we're correctly parsing the intel
syntax the pushad/popad don't match properly. I've reimplemented that fix using
a MnemonicAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/X86')
| -rw-r--r-- | test/MC/X86/x86_errors.s | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s index 6e14d62fda..a974233d2f 100644 --- a/test/MC/X86/x86_errors.s +++ b/test/MC/X86/x86_errors.s @@ -28,3 +28,6 @@ lea (%rsp, %rbp, $4), %rax // rdar://10423777 // 64: error: index register is 32-bit, but base register is 64-bit movq (%rsi,%ecx),%xmm0 + +// 32: error: invalid operand for instruction +outb al, 4 |