Allow multiclass def names to contain "#NAME"" where TableGen replaces

#NAME# with the name of the defm instantiating the multiclass.  This is
useful for AVX instruction naming where a "V" prefix is standard
throughout the ISA.  For example:

multiclass SSE_AVX_Inst<...> {
   def SS : Instr<...>;
   def SD : Instr<...>;
   def PS : Instr<...>;
   def PD : Instr<...>;

   def V#NAME#SS : Instr<...>;
   def V#NAME#SD : Instr<...>;
   def V#NAME#PS : Instr<...>;
   def V#NAME#PD : Instr<...>;
}

defm ADD : SSE_AVX_Inst<...>;

Results in 

ADDSS
ADDSD
ADDPS
ADDPD

VADDSS
VADDSD
VADDPS
VADDPD


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70979 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 0 deletions

diff --git a/test/TableGen/MultiClassDefName.td b/test/TableGen/MultiClassDefName.td
new file mode 100644
index 0000000000..2e71f7d061
--- /dev/null
+++ b/test/TableGen/MultiClassDefName.td
@@ -0,0 +1,12 @@
+// RUN: tblgen %s | grep WorldHelloCC | count 1
+
+class C<string n> {
+  string name = n;
+}
+
+multiclass Names<string n, string m> {
+   def CC : C<n>;
+   def World#NAME#CC : C<m>;
+}
+
+defm Hello : Names<"hello", "world">;