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authorChad Rosier <mcrosier@apple.com>2012-06-06 17:22:40 +0000
committerChad Rosier <mcrosier@apple.com>2012-06-06 17:22:40 +0000
commit8b421c8eb2c41ee66cd1023bc7c262bdfaea481d (patch)
tree60982273279726f4727b1a55971c67e21a87ddad /test/Transforms/InstCombine/and-fcmp.ll
parent461e7eaa6fc52f96d01f7e1a5c357eae79e52508 (diff)
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Fix combine of uno && ord -> false so that the ordering of the fcmps doesn't
matter. rdar://11579835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158084 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine/and-fcmp.ll')
-rw-r--r--test/Transforms/InstCombine/and-fcmp.ll10
1 files changed, 10 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/and-fcmp.ll b/test/Transforms/InstCombine/and-fcmp.ll
index f6a226e3b5..282e88b53d 100644
--- a/test/Transforms/InstCombine/and-fcmp.ll
+++ b/test/Transforms/InstCombine/and-fcmp.ll
@@ -56,3 +56,13 @@ define zeroext i8 @t5(float %x, float %y) nounwind {
; CHECK: t5
; CHECK: ret i8 0
}
+
+define zeroext i8 @t6(float %x, float %y) nounwind {
+ %a = fcmp uno float %x, %y
+ %b = fcmp ord float %x, %y
+ %c = and i1 %a, %b
+ %retval = zext i1 %c to i8
+ ret i8 %retval
+; CHECK: t6
+; CHECK: ret i8 0
+}