diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-23 17:39:52 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-23 17:39:52 +0000 |
| commit | 72847f3057a7d82be087d3aad7d13b7719409a32 (patch) | |
| tree | eb43c8ccca87249cc68ffbd0827d5ed5d30ce757 /test/Transforms/InstCombine/cast.ll | |
| parent | 9dc06bd431c826f068a5217718e2171303782f7a (diff) | |
| download | llvm-72847f3057a7d82be087d3aad7d13b7719409a32.tar.gz llvm-72847f3057a7d82be087d3aad7d13b7719409a32.tar.bz2 llvm-72847f3057a7d82be087d3aad7d13b7719409a32.tar.xz | |
Reapply r155136 after fixing PR12599.
Original commit message:
Defer some shl transforms to DAGCombine.
The shl instruction is used to represent multiplication by a constant
power of two as well as bitwise left shifts. Some InstCombine
transformations would turn an shl instruction into a bit mask operation,
making it difficult for later analysis passes to recognize the
constsnt multiplication.
Disable those shl transformations, deferring them to DAGCombine time.
An 'shl X, C' instruction is now treated mostly the same was as 'mul X, C'.
These transformations are deferred:
(X >>? C) << C --> X & (-1 << C) (When X >> C has multiple uses)
(X >>? C1) << C2 --> X << (C2-C1) & (-1 << C2) (When C2 > C1)
(X >>? C1) << C2 --> X >>? (C1-C2) & (-1 << C2) (When C1 > C2)
The corresponding exact transformations are preserved, just like
div-exact + mul:
(X >>?,exact C) << C --> X
(X >>?,exact C1) << C2 --> X << (C2-C1)
(X >>?,exact C1) << C2 --> X >>?,exact (C1-C2)
The disabled transformations could also prevent the instruction selector
from recognizing rotate patterns in hash functions and cryptographic
primitives. I have a test case for that, but it is too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155362 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine/cast.ll')
| -rw-r--r-- | test/Transforms/InstCombine/cast.ll | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll index 19d5a0ae77..7cf63e8ce1 100644 --- a/test/Transforms/InstCombine/cast.ll +++ b/test/Transforms/InstCombine/cast.ll @@ -457,10 +457,12 @@ define i64 @test50(i64 %A) { %E = sext i32 %D to i64 ret i64 %E ; CHECK: @test50 -; CHECK-NEXT: shl i64 %A, 30 +; lshr+shl will be handled by DAGCombine. +; CHECK-NEXT: lshr i64 %A, 2 +; CHECK-NEXT: shl i64 %a, 32 ; CHECK-NEXT: add i64 {{.*}}, -4294967296 -; CHECK-NEXT: %sext = ashr i64 {{.*}}, 32 -; CHECK-NEXT: ret i64 %sext +; CHECK-NEXT: %E = ashr exact i64 {{.*}}, 32 +; CHECK-NEXT: ret i64 %E } define i64 @test51(i64 %A, i1 %cond) { |