Revert "Combine bit test + conditional or into simple math"

It is causing stage2 builds to fail, let's get them running again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179750 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 79 deletions

diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll
index 97bd8fe70a..cc3aacdce3 100644
--- a/test/Transforms/InstCombine/select.ll
+++ b/test/Transforms/InstCombine/select.ll
@@ -863,82 +863,3 @@ while.body:
 ; CHECK: @test64
 ; CHECK-NOT: select
 }
-
-; CHECK: @select_icmp_eq_and_1_0_or_2
-; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
-  %and = and i32 %x, 1
-  %cmp = icmp eq i32 %and, 0
-  %or = or i32 %y, 2
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}
-
-; CHECK: @select_icmp_eq_and_32_0_or_8
-; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
-  %and = and i32 %x, 32
-  %cmp = icmp eq i32 %and, 0
-  %or = or i32 %y, 8
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}
-
-; CHECK: @select_icmp_ne_0_and_4096_or_4096
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
-; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
-  %and = and i32 %x, 4096
-  %cmp = icmp ne i32 0, %and
-  %or = or i32 %y, 4096
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}
-
-; CHECK: @select_icmp_eq_and_4096_0_or_4096
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
-  %and = and i32 %x, 4096
-  %cmp = icmp eq i32 %and, 0
-  %or = or i32 %y, 4096
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}
-
-; CHECK: @select_icmp_ne_0_and_4096_or_32
-; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32
-; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
-  %and = and i32 %x, 4096
-  %cmp = icmp ne i32 0, %and
-  %or = or i32 %y, 32
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}
-
-; CHECK: @select_icmp_ne_0_and_32_or_4096
-; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096
-; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
-; CHECK-NEXT: ret i32 [[OR]]
-define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
-  %and = and i32 %x, 32
-  %cmp = icmp ne i32 0, %and
-  %or = or i32 %y, 4096
-  %select = select i1 %cmp, i32 %y, i32 %or
-  ret i32 %select
-}