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authorNadav Rotem <nadav.rotem@intel.com>2011-12-05 06:29:09 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-12-05 06:29:09 +0000
commit1608769abeb1430dc34f31ffac0d9850f99ae36a (patch)
tree7834f9a415e0348f155f2834c40171c3b13d60ed /test
parent8e1b12ae68cd6ae5180cb300a05bae5ddf0c49ae (diff)
downloadllvm-1608769abeb1430dc34f31ffac0d9850f99ae36a.tar.gz
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Add support for vectors of pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/pointer-vector.ll138
-rw-r--r--test/CodeGen/X86/vector-gep.ll77
-rw-r--r--test/Feature/const_pv.ll8
-rw-r--r--test/Feature/global_pv.ll14
-rw-r--r--test/Transforms/InstCombine/vector_gep1.ll37
-rw-r--r--test/Transforms/InstSimplify/vector_gep.ll8
6 files changed, 282 insertions, 0 deletions
diff --git a/test/CodeGen/X86/pointer-vector.ll b/test/CodeGen/X86/pointer-vector.ll
new file mode 100644
index 0000000000..9c1c521312
--- /dev/null
+++ b/test/CodeGen/X86/pointer-vector.ll
@@ -0,0 +1,138 @@
+; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
+; RUN: opt -instsimplify %s -disable-output
+
+;CHECK: SHUFF0
+define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind {
+entry:
+ %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <8 x i32> <i32 2, i32 7, i32 1, i32 2, i32 4, i32 5, i32 1, i32 1>
+;CHECK: pshufd
+ ret <8 x i32*> %G
+;CHECK: ret
+}
+
+;CHECK: SHUFF1
+define <4 x i32*> @SHUFF1(<4 x i32*> %ptrv) nounwind {
+entry:
+ %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <4 x i32> <i32 2, i32 7, i32 7, i32 2>
+;CHECK: pshufd
+ ret <4 x i32*> %G
+;CHECK: ret
+}
+
+;CHECK: SHUFF3
+define <4 x i8*> @SHUFF3(<4 x i8*> %ptrv) nounwind {
+entry:
+ %G = shufflevector <4 x i8*> %ptrv, <4 x i8*> undef, <4 x i32> <i32 2, i32 7, i32 1, i32 2>
+;CHECK: pshufd
+ ret <4 x i8*> %G
+;CHECK: ret
+}
+
+;CHECK: LOAD0
+define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind {
+entry:
+ %G = load <4 x i8*>* %p
+;CHECK: movaps
+ ret <4 x i8*> %G
+;CHECK: ret
+}
+
+;CHECK: LOAD1
+define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind {
+entry:
+ %G = load <4 x i8*>* %p
+;CHECK: movdqa
+;CHECK: pshufd
+;CHECK: movdqa
+ %T = shufflevector <4 x i8*> %G, <4 x i8*> %G, <4 x i32> <i32 7, i32 1, i32 4, i32 3>
+ store <4 x i8*> %T, <4 x i8*>* %p
+ ret <4 x i8*> %G
+;CHECK: ret
+}
+
+;CHECK: LOAD2
+define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind {
+entry:
+ %I = alloca <4 x i8*>
+;CHECK: sub
+ %G = load <4 x i8*>* %p
+;CHECK: movaps
+ store <4 x i8*> %G, <4 x i8*>* %I
+;CHECK: movaps
+ %Z = load <4 x i8*>* %I
+ ret <4 x i8*> %Z
+;CHECK: add
+;CHECK: ret
+}
+
+;CHECK: INT2PTR0
+define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind {
+entry:
+ %G = load <4 x i8*>* %p
+;CHECK: movl
+;CHECK: movaps
+ %K = ptrtoint <4 x i8*> %G to <4 x i32>
+;CHECK: ret
+ ret <4 x i32> %K
+}
+
+;CHECK: INT2PTR1
+define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
+entry:
+ %G = load <4 x i8>* %p
+;CHECK: movl
+;CHECK: movd
+;CHECK: pshufb
+;CHECK: pand
+ %K = inttoptr <4 x i8> %G to <4 x i32*>
+;CHECK: ret
+ ret <4 x i32*> %K
+}
+
+;CHECK: BITCAST0
+define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind {
+entry:
+ %G = load <4 x i8*>* %p
+;CHECK: movl
+ %T = bitcast <4 x i8*> %G to <4 x i32*>
+;CHECK: movaps
+;CHECK: ret
+ ret <4 x i32*> %T
+}
+
+;CHECK: BITCAST1
+define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
+entry:
+ %G = load <2 x i8*>* %p
+;CHECK: movl
+;CHECK: movd
+;CHECK: pinsrd
+ %T = bitcast <2 x i8*> %G to <2 x i32*>
+;CHECK: ret
+ ret <2 x i32*> %T
+}
+
+;CHECK: ICMP0
+define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
+entry:
+ %g0 = load <4 x i8*>* %p0
+ %g1 = load <4 x i8*>* %p1
+ %k = icmp sgt <4 x i8*> %g0, %g1
+ ;CHECK: pcmpgtd
+ %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
+ ret <4 x i32> %j
+ ;CHECK: ret
+}
+
+;CHECK: ICMP1
+define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
+entry:
+ %g0 = load <4 x i8*>* %p0
+ %g1 = load <4 x i8*>* %p1
+ %k = icmp eq <4 x i8*> %g0, %g1
+ ;CHECK: pcmpeqd
+ %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
+ ret <4 x i32> %j
+ ;CHECK: ret
+}
+
diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll
new file mode 100644
index 0000000000..d032eda88b
--- /dev/null
+++ b/test/CodeGen/X86/vector-gep.ll
@@ -0,0 +1,77 @@
+; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s
+; RUN: opt -instsimplify %s -disable-output
+
+;CHECK: AGEP0
+define <4 x i32*> @AGEP0(i32* %ptr) nounwind {
+entry:
+ %vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0
+ %vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1
+ %vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2
+ %vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3
+;CHECK: pslld
+;CHECK: padd
+ %A2 = getelementptr <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+;CHECK: pslld
+;CHECK: padd
+ %A3 = getelementptr <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233>
+ ret <4 x i32*> %A3
+;CHECK: ret
+}
+
+;CHECK: AGEP1
+define i32 @AGEP1(<4 x i32*> %param) nounwind {
+entry:
+;CHECK: pslld
+;CHECK: padd
+ %A2 = getelementptr <4 x i32*> %param, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ %k = extractelement <4 x i32*> %A2, i32 3
+ %v = load i32* %k
+ ret i32 %v
+;CHECK: ret
+}
+
+;CHECK: AGEP2
+define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind {
+entry:
+;CHECK: pslld
+;CHECK: padd
+ %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off
+ %k = extractelement <4 x i32*> %A2, i32 3
+ %v = load i32* %k
+ ret i32 %v
+;CHECK: ret
+}
+
+;CHECK: AGEP3
+define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind {
+entry:
+;CHECK: pslld
+;CHECK: padd
+ %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off
+ %v = alloca i32
+ %k = insertelement <4 x i32*> %A2, i32* %v, i32 3
+ ret <4 x i32*> %k
+;CHECK: ret
+}
+
+;CHECK: AGEP4
+define <4 x i8*> @AGEP4(<4 x i8*> %param, <4 x i32> %off) nounwind {
+entry:
+;CHECK: pslld
+;CHECK: padd
+ %A = getelementptr <4 x i8*> %param, <4 x i32> %off
+ ret <4 x i8*> %A
+;CHECK: ret
+}
+
+;CHECK: AGEP5
+define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind {
+entry:
+;CHECK: pslld
+;CHECK: padd
+ %A = getelementptr <4 x i8*> %param, <4 x i8> %off
+ ret <4 x i8*> %A
+;CHECK: ret
+}
+
+
diff --git a/test/Feature/const_pv.ll b/test/Feature/const_pv.ll
new file mode 100644
index 0000000000..6fd6abdccf
--- /dev/null
+++ b/test/Feature/const_pv.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as %s -disable-output
+@G = constant <3 x i64> ptrtoint (<3 x i8*> <i8* null, i8* null, i8* null> to <3 x i64>)
+
+@G1 = global i8 zeroinitializer
+@g = constant <2 x i8*> getelementptr (<2 x i8*> <i8* @G1, i8* @G1>, <2 x i32> <i32 0, i32 0>)
+
+@t = constant <2 x i1> icmp ((<2 x i32> ptrtoint (<2 x i8*> zeroinitializer to <2 x i32>), <2 x i32> zeroinitializer )
+
diff --git a/test/Feature/global_pv.ll b/test/Feature/global_pv.ll
new file mode 100644
index 0000000000..d257ec077a
--- /dev/null
+++ b/test/Feature/global_pv.ll
@@ -0,0 +1,14 @@
+; RUN: opt -instcombine -S -o - %s | llvm-as
+; RUN: opt -instcombine -globalopt -S -o - %s | llvm-as
+@G1 = global i32 zeroinitializer
+@G2 = global i32 zeroinitializer
+@g = global <2 x i32*> zeroinitializer
+%0 = type { i32, void ()* }
+@llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @test }]
+define internal void @test() {
+ %A = insertelement <2 x i32*> undef, i32* @G1, i32 0
+ %B = insertelement <2 x i32*> %A, i32* @G2, i32 1
+ store <2 x i32*> %B, <2 x i32*>* @g
+ ret void
+}
+
diff --git a/test/Transforms/InstCombine/vector_gep1.ll b/test/Transforms/InstCombine/vector_gep1.ll
new file mode 100644
index 0000000000..6523622995
--- /dev/null
+++ b/test/Transforms/InstCombine/vector_gep1.ll
@@ -0,0 +1,37 @@
+; RUN: opt -instcombine %s -disable-output
+; RUN: opt -instsimplify %s -disable-output
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@G1 = global i8 zeroinitializer
+
+define <2 x i1> @test(<2 x i8*> %a, <2 x i8*> %b) {
+ %A = icmp eq <2 x i8*> %a, %b
+ ret <2 x i1> %A
+}
+
+define <2 x i1> @test2(<2 x i8*> %a) {
+ %A = inttoptr <2 x i32> <i32 1, i32 2> to <2 x i8*>
+ %B = icmp ult <2 x i8*> %A, zeroinitializer
+ ret <2 x i1> %B
+}
+
+define <2 x i1> @test3(<2 x i8*> %a) {
+ %g = getelementptr <2 x i8*> %a, <2 x i32> <i32 1, i32 0>
+ %B = icmp ult <2 x i8*> %g, zeroinitializer
+ ret <2 x i1> %B
+}
+
+define <1 x i1> @test4(<1 x i8*> %a) {
+ %g = getelementptr <1 x i8*> %a, <1 x i32> <i32 1>
+ %B = icmp ult <1 x i8*> %g, zeroinitializer
+ ret <1 x i1> %B
+}
+
+define <2 x i1> @test5(<2 x i8*> %a) {
+ %w = getelementptr <2 x i8*> %a, <2 x i32> zeroinitializer
+ %e = getelementptr <2 x i8*> %w, <2 x i32> <i32 5, i32 9>
+ %g = getelementptr <2 x i8*> %e, <2 x i32> <i32 1, i32 0>
+ %B = icmp ult <2 x i8*> %g, zeroinitializer
+ ret <2 x i1> %B
+}
diff --git a/test/Transforms/InstSimplify/vector_gep.ll b/test/Transforms/InstSimplify/vector_gep.ll
new file mode 100644
index 0000000000..f65260e00f
--- /dev/null
+++ b/test/Transforms/InstSimplify/vector_gep.ll
@@ -0,0 +1,8 @@
+;RUN: opt -instsimplify %s -disable-output
+declare void @helper(<2 x i8*>)
+define void @test(<2 x i8*> %a) {
+ %A = getelementptr <2 x i8*> %a, <2 x i32> <i32 0, i32 0>
+ call void @helper(<2 x i8*> %A)
+ ret void
+}
+