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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:29 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:29 +0000 |
commit | 3e38856f04a01651819c6bc16fac4434a5d2b4c6 (patch) | |
tree | 0a53471776dac44933dea3e3816270b1e5809b16 /test | |
parent | 836c5133c66edecedeaa79448964b4c103f99271 (diff) | |
download | llvm-3e38856f04a01651819c6bc16fac4434a5d2b4c6.tar.gz llvm-3e38856f04a01651819c6bc16fac4434a5d2b4c6.tar.bz2 llvm-3e38856f04a01651819c6bc16fac4434a5d2b4c6.tar.xz |
R600/SI: Move patterns to match add / sub to scalar instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/R600/32-bit-local-address-space.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/R600/address-space.ll | 7 | ||||
-rw-r--r-- | test/CodeGen/R600/gep-address-space.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/R600/rotr.ll | 13 |
4 files changed, 24 insertions, 20 deletions
diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll index 63909f0b09..7a126878be 100644 --- a/test/CodeGen/R600/32-bit-local-address-space.ll +++ b/test/CodeGen/R600/32-bit-local-address-space.ll @@ -20,8 +20,9 @@ entry: } ; CHECK-LABEL: @local_address_gep -; CHECK: V_ADD_I32_e{{32|64}} [[PTR:v[0-9]]] -; CHECK: DS_READ_B32 [[PTR]] +; CHECK: S_ADD_I32 [[SPTR:s[0-9]]] +; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: DS_READ_B32 [[VPTR]] define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) { entry: %0 = getelementptr i32 addrspace(3)* %in, i32 %offset @@ -31,8 +32,9 @@ entry: } ; CHECK-LABEL: @local_address_gep_const_offset -; CHECK: V_ADD_I32_e{{32|64}} [[PTR:v[0-9]]] -; CHECK: DS_READ_B32 [[PTR]] +; CHECK: S_ADD_I32 [[SPTR:s[0-9]]] +; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: DS_READ_B32 [[VPTR]] define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = getelementptr i32 addrspace(3)* %in, i32 1 diff --git a/test/CodeGen/R600/address-space.ll b/test/CodeGen/R600/address-space.ll index 633101f42a..1fc616a4ed 100644 --- a/test/CodeGen/R600/address-space.ll +++ b/test/CodeGen/R600/address-space.ll @@ -5,9 +5,10 @@ %struct.foo = type { [3 x float], [3 x float] } ; CHECK-LABEL: @do_as_ptr_calcs: -; CHECK: V_ADD_I32_e64 {{v[0-9]+}}, -; CHECK: V_ADD_I32_e64 [[REG1:v[0-9]+]], -; CHECK: DS_READ_B32 [[REG1]], +; CHECK: S_ADD_I32 {{s[0-9]+}}, +; CHECK: S_ADD_I32 [[SREG1:s[0-9]+]], +; CHECK: V_MOV_B32_e32 [[VREG1:v[0-9]+]], [[SREG1]] +; CHECK: DS_READ_B32 [[VREG1]], define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind { entry: %x = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll index 934b5a5956..4ea21dde8a 100644 --- a/test/CodeGen/R600/gep-address-space.ll +++ b/test/CodeGen/R600/gep-address-space.ll @@ -2,7 +2,7 @@ define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind { ; CHECK-LABEL @use_gep_address_space: -; CHECK: ADD_I32 +; CHECK: S_ADD_I32 %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16 store i32 99, i32 addrspace(3)* %p ret void @@ -10,10 +10,10 @@ define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind { define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind { ; CHECK-LABEL: @gep_as_vector_v4: -; CHECK: V_ADD_I32 -; CHECK: V_ADD_I32 -; CHECK: V_ADD_I32 -; CHECK: V_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 %p = getelementptr <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0 %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1 @@ -28,8 +28,8 @@ define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind { ; CHECK-LABEL: @gep_as_vector_v2: -; CHECK: V_ADD_I32 -; CHECK: V_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 %p = getelementptr <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16> %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0 %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1 diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index 0a68d7e16e..edf7aeebea 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; R600-CHECK: @rotr +; R600-CHECK-LABEL: @rotr: ; R600-CHECK: BIT_ALIGN_INT -; SI-CHECK: @rotr +; SI-CHECK-LABEL: @rotr: ; SI-CHECK: V_ALIGNBIT_B32 define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: @@ -16,15 +16,16 @@ entry: ret void } -; R600-CHECK: @rotl +; R600-CHECK-LABEL: @rotl: ; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x ; R600-CHECK-NEXT: 32 ; R600-CHECK: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} -; SI-CHECK: @rotl -; SI-CHECK: V_SUB_I32_e64 [[DST:v[0-9]+]], 32, {{[sv][0-9]+}} -; SI-CHECK: V_ALIGNBIT_B32 {{v[0-9]+, [sv][0-9]+, v[0-9]+}}, [[DST]] +; SI-CHECK-LABEL: @rotl: +; SI-CHECK: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} +; SI-CHECK: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]] +; SI-CHECK: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]] define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = shl i32 %x, %y |