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| author | Chandler Carruth <chandlerc@gmail.com> | 2011-12-24 12:12:34 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2011-12-24 12:12:34 +0000 |
| commit | 7782102c70fdfd48776f05099eb67dd268cfc222 (patch) | |
| tree | bfdaa8f63ef7445489f0568106f80b7c1829e701 /test | |
| parent | 3d636ea8edf9332ab5ab2d92f7ea5c7444e88757 (diff) | |
| download | llvm-7782102c70fdfd48776f05099eb67dd268cfc222.tar.gz llvm-7782102c70fdfd48776f05099eb67dd268cfc222.tar.bz2 llvm-7782102c70fdfd48776f05099eb67dd268cfc222.tar.xz | |
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/bmi.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/clz.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/lzcnt.ll | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index e79c92f1e2..43c47c0fa8 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -9,7 +9,7 @@ define i8 @t1(i8 %x) nounwind { %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false ) ret i8 %tmp ; CHECK: t1: -; CHECK: tzcntw +; CHECK: tzcntl } define i16 @t2(i16 %x) nounwind { @@ -37,7 +37,7 @@ define i8 @t5(i8 %x) nounwind { %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true ) ret i8 %tmp ; CHECK: t5: -; CHECK: tzcntw +; CHECK: tzcntl } define i16 @t6(i16 %x) nounwind { diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index 6f4d305385..763079f344 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -13,7 +13,7 @@ define i8 @cttz_i8(i8 %x) { %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true ) ret i8 %tmp ; CHECK: cttz_i8: -; CHECK: bsfw +; CHECK: bsfl ; CHECK-NOT: cmov ; CHECK: ret } diff --git a/test/CodeGen/X86/lzcnt.ll b/test/CodeGen/X86/lzcnt.ll index eb010d7f5a..2faa24a9a5 100644 --- a/test/CodeGen/X86/lzcnt.ll +++ b/test/CodeGen/X86/lzcnt.ll @@ -9,7 +9,7 @@ define i8 @t1(i8 %x) nounwind { %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false ) ret i8 %tmp ; CHECK: t1: -; CHECK: lzcntw +; CHECK: lzcntl } define i16 @t2(i16 %x) nounwind { @@ -37,7 +37,7 @@ define i8 @t5(i8 %x) nounwind { %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true ) ret i8 %tmp ; CHECK: t5: -; CHECK: lzcntw +; CHECK: lzcntl } define i16 @t6(i16 %x) nounwind { |