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author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:44 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:44 +0000 |
commit | 9157d273c4b66084c0fd6aa01075ce55984bd868 (patch) | |
tree | fd4d23077bd2109e1fb004dac50178b461f200eb /test | |
parent | 8d6df7ac7309bfbd1bfe34b7626b15ead2bd2702 (diff) | |
download | llvm-9157d273c4b66084c0fd6aa01075ce55984bd868.tar.gz llvm-9157d273c4b66084c0fd6aa01075ce55984bd868.tar.bz2 llvm-9157d273c4b66084c0fd6aa01075ce55984bd868.tar.xz |
Merging r203818:
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r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines
R600: LDS instructions shouldn't implicitly define OQAP
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.
This fixes a hang in the opencv MedianFilter tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/R600/lds-oqap-crash.ll | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/CodeGen/R600/lds-oqap-crash.ll b/test/CodeGen/R600/lds-oqap-crash.ll new file mode 100644 index 0000000000..79591506e8 --- /dev/null +++ b/test/CodeGen/R600/lds-oqap-crash.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s + +; The test is for a bug in R600EmitClauseMarkers.cpp where this pass +; was searching for a use of the OQAP register in order to determine +; if an LDS instruction could fit in the current clause, but never finding +; one. This created an infinite loop and hung the compiler. +; +; The LDS instruction should not have been defining OQAP in the first place, +; because the LDS instructions are pseudo instructions and the OQAP +; reads and writes are bundled together in the same instruction. + +; CHECK: @lds_crash +define void @lds_crash(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %a, i32 %b, i32 %c) { +entry: + %0 = load i32 addrspace(3)* %in + ; This block needs to be > 115 ISA instructions to hit the bug, + ; so we'll use udiv instructions. + %div0 = udiv i32 %0, %b + %div1 = udiv i32 %div0, %a + %div2 = udiv i32 %div1, 11 + %div3 = udiv i32 %div2, %a + %div4 = udiv i32 %div3, %b + %div5 = udiv i32 %div4, %c + %div6 = udiv i32 %div5, %div0 + %div7 = udiv i32 %div6, %div1 + store i32 %div7, i32 addrspace(1)* %out + ret void +} |