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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-08-11 07:55:09 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-08-11 07:55:09 +0000 |
commit | fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e (patch) | |
tree | dd79127c979855b250e8b8651917f7142792cd48 /test | |
parent | 5b854f1ea55601790d9191c9720e77da35095340 (diff) | |
download | llvm-fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e.tar.gz llvm-fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e.tar.bz2 llvm-fac4a4eb7dfbfc90ae1d5c7d6c39a2d89a33c30e.tar.xz |
AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.
Added a test for shuffles using VPERM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/avx512-shuffle.ll | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll new file mode 100644 index 0000000000..9f3d86a5e6 --- /dev/null +++ b/test/CodeGen/X86/avx512-shuffle.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; CHECK: LCP +; CHECK: .long 2 +; CHECK: .long 5 +; CHECK: .long 0 +; CHECK: .long 0 +; CHECK: .long 7 +; CHECK: .long 0 +; CHECK: .long 10 +; CHECK: .long 1 +; CHECK: .long 0 +; CHECK: .long 5 +; CHECK: .long 0 +; CHECK: .long 4 +; CHECK: .long 7 +; CHECK: .long 0 +; CHECK: .long 10 +; CHECK: .long 1 +; CHECK: test1: +; CHECK: vpermps +; CHECK: ret +define <16 x float> @test1(<16 x float> %a) nounwind { + %c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1> + ret <16 x float> %c +} + +; CHECK: test2: +; CHECK: vpermd +; CHECK: ret +define <16 x i32> @test2(<16 x i32> %a) nounwind { + %c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1> + ret <16 x i32> %c +} + +; CHECK: test3: +; CHECK: vpermq +; CHECK: ret +define <8 x i64> @test3(<8 x i64> %a) nounwind { + %c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1> + ret <8 x i64> %c +} + +; CHECK: test4: +; CHECK: vpermpd +; CHECK: ret +define <8 x double> @test4(<8 x double> %a) nounwind { + %c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x double> %c +} + +; CHECK: test5: +; CHECK: vpermi2pd +; CHECK: ret +define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind { + %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5> + ret <8 x double> %c +} + +; CHECK: test6: +; CHECK: vpermq $30 +; CHECK: ret +define <8 x i64> @test6(<8 x i64> %a) nounwind { + %c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4> + ret <8 x i64> %c +} + |