diff options
author | Justin Holewinski <jholewinski@nvidia.com> | 2014-06-27 18:35:37 +0000 |
---|---|---|
committer | Justin Holewinski <jholewinski@nvidia.com> | 2014-06-27 18:35:37 +0000 |
commit | 10da1651ed7428b35ee89e0dc72ec177bf7041aa (patch) | |
tree | 2818dd545daae6db38c2d6cd295b7de2b061e262 /test | |
parent | 508c80f11f2f52f549caf86f9f6e07d07cea6006 (diff) | |
download | llvm-10da1651ed7428b35ee89e0dc72ec177bf7041aa.tar.gz llvm-10da1651ed7428b35ee89e0dc72ec177bf7041aa.tar.bz2 llvm-10da1651ed7428b35ee89e0dc72ec177bf7041aa.tar.xz |
[NVPTX] Implement fma and imad contraction as target DAGCombiner patterns
This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211935 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/NVPTX/imad.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/NVPTX/mulwide.ll | 37 |
2 files changed, 46 insertions, 0 deletions
diff --git a/test/CodeGen/NVPTX/imad.ll b/test/CodeGen/NVPTX/imad.ll new file mode 100644 index 0000000000..67421c7cac --- /dev/null +++ b/test/CodeGen/NVPTX/imad.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +; CHECK: imad +define i32 @imad(i32 %a, i32 %b, i32 %c) { +; CHECK: mad.lo.s32 + %val0 = mul i32 %a, %b + %val1 = add i32 %val0, %c + ret i32 %val1 +} diff --git a/test/CodeGen/NVPTX/mulwide.ll b/test/CodeGen/NVPTX/mulwide.ll new file mode 100644 index 0000000000..927946c8fb --- /dev/null +++ b/test/CodeGen/NVPTX/mulwide.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +; CHECK: mulwide16 +define i32 @mulwide16(i16 %a, i16 %b) { +; CHECK: mul.wide.s16 + %val0 = sext i16 %a to i32 + %val1 = sext i16 %b to i32 + %val2 = mul i32 %val0, %val1 + ret i32 %val2 +} + +; CHECK: mulwideu16 +define i32 @mulwideu16(i16 %a, i16 %b) { +; CHECK: mul.wide.u16 + %val0 = zext i16 %a to i32 + %val1 = zext i16 %b to i32 + %val2 = mul i32 %val0, %val1 + ret i32 %val2 +} + +; CHECK: mulwide32 +define i64 @mulwide32(i32 %a, i32 %b) { +; CHECK: mul.wide.s32 + %val0 = sext i32 %a to i64 + %val1 = sext i32 %b to i64 + %val2 = mul i64 %val0, %val1 + ret i64 %val2 +} + +; CHECK: mulwideu32 +define i64 @mulwideu32(i32 %a, i32 %b) { +; CHECK: mul.wide.u32 + %val0 = zext i32 %a to i64 + %val1 = zext i32 %b to i64 + %val2 = mul i64 %val0, %val1 + ret i64 %val2 +} |