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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
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| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
| commit | 52981c4b6016d9f0e295e0771ec0a50dd073b4b3 (patch) | |
| tree | ccb38cb2e26c468e41f6c039be8acb00bd60b19b /unittests/ADT | |
| parent | 1479c9bb392325688b72e5829bbb7939c4a079a4 (diff) | |
| download | llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.gz llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.bz2 llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.xz | |
I optimized the following patterns:
sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'unittests/ADT')
0 files changed, 0 insertions, 0 deletions