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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 04:50:36 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 04:50:36 +0000 |
| commit | ae1920b1efa72c1789d562df4746110d0c2e10bd (patch) | |
| tree | 22d7d8690b9997d57f32d4a0fd850b3d99dd0846 /utils/TableGen/AsmWriterEmitter.cpp | |
| parent | 393c4047c05b6d7b5851d339e51bb2cc35f630c2 (diff) | |
| download | llvm-ae1920b1efa72c1789d562df4746110d0c2e10bd.tar.gz llvm-ae1920b1efa72c1789d562df4746110d0c2e10bd.tar.bz2 llvm-ae1920b1efa72c1789d562df4746110d0c2e10bd.tar.xz | |
Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.
Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/AsmWriterEmitter.cpp')
| -rw-r--r-- | utils/TableGen/AsmWriterEmitter.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index bfc63c0cf8..818053a3c4 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -805,16 +805,16 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) { O << " case RC_" << Name << ":\n"; // Emit the register list now. - unsigned IE = RC.Elements.size(); + unsigned IE = RC.getOrder().size(); if (IE == 1) { - O << " if (Reg == " << getQualifiedName(RC.Elements[0]) << ")\n"; + O << " if (Reg == " << getQualifiedName(RC.getOrder()[0]) << ")\n"; O << " return true;\n"; } else { O << " switch (Reg) {\n"; O << " default: break;\n"; for (unsigned II = 0; II != IE; ++II) { - Record *Reg = RC.Elements[II]; + Record *Reg = RC.getOrder()[II]; O << " case " << getQualifiedName(Reg) << ":\n"; } |