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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-09 22:15:00 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-09 22:15:00 +0000 |
commit | ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe (patch) | |
tree | 494cae81f83bb8297bb53ec1ec62d966da05aec3 /utils/TableGen/CodeGenRegisters.h | |
parent | da2be824346c316c6fc840de7b8493e3d587e785 (diff) | |
download | llvm-ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe.tar.gz llvm-ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe.tar.bz2 llvm-ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe.tar.xz |
Compute a backwards SubReg -> SubRegIndex map for each register.
This mapping is for internal use by TableGen. It will not be exposed in
the generated files.
Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.
For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenRegisters.h')
-rw-r--r-- | utils/TableGen/CodeGenRegisters.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index b0f8f4683f..dce08b4ff5 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -113,6 +113,12 @@ namespace llvm { void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, CodeGenRegBank&) const; + // Return the sub-register index naming Reg as a sub-register of this + // register. Returns NULL if Reg is not a sub-register. + CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { + return SubReg2Idx.lookup(Reg); + } + // List of super-registers in topological order, small to large. typedef std::vector<const CodeGenRegister*> SuperRegList; @@ -157,6 +163,7 @@ namespace llvm { bool SubRegsComplete; SubRegMap SubRegs; SuperRegList SuperRegs; + DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx; RegUnitList RegUnits; }; |