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| author | Owen Anderson <resistor@mac.com> | 2011-06-27 21:06:21 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-06-27 21:06:21 +0000 |
| commit | bea6f615eefae279e53bbb63a31d2c3c67274c45 (patch) | |
| tree | 4c5b33c01d807a99de8411304c63cfdb5583b259 /utils/TableGen/FastISelEmitter.cpp | |
| parent | d1f0bbee189ea7cd18d03c4f9f55d0a33b070814 (diff) | |
| download | llvm-bea6f615eefae279e53bbb63a31d2c3c67274c45.tar.gz llvm-bea6f615eefae279e53bbb63a31d2c3c67274c45.tar.bz2 llvm-bea6f615eefae279e53bbb63a31d2c3c67274c45.tar.xz | |
Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/FastISelEmitter.cpp')
| -rw-r--r-- | utils/TableGen/FastISelEmitter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index f946ac73ca..f54e8df40f 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -248,6 +248,8 @@ struct OperandsSignature { // For now, the only other thing we accept is register operands. const CodeGenRegisterClass *RC = 0; + if (OpLeafRec->isSubClassOf("RegisterOperand")) + OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) @@ -454,6 +456,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { std::string SubRegNo; if (Op->getName() != "EXTRACT_SUBREG") { Record *Op0Rec = II.Operands[0].Rec; + if (Op0Rec->isSubClassOf("RegisterOperand")) + Op0Rec = Op0Rec->getValueAsDef("RegClass"); if (!Op0Rec->isSubClassOf("RegisterClass")) continue; DstRC = &Target.getRegisterClass(Op0Rec); |