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| author | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:25 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:25 +0000 |
| commit | fe05d98c253676d1ae6e0f03efde6b75fdae105d (patch) | |
| tree | f60826629a442cb274bdad112a707241e65175f1 /utils/TableGen/SubtargetEmitter.cpp | |
| parent | d494a3bfc5a4c9a335775669cfd6d804bc88d00a (diff) | |
| download | llvm-fe05d98c253676d1ae6e0f03efde6b75fdae105d.tar.gz llvm-fe05d98c253676d1ae6e0f03efde6b75fdae105d.tar.bz2 llvm-fe05d98c253676d1ae6e0f03efde6b75fdae105d.tar.xz | |
Cleanup TableGen subtarget emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/SubtargetEmitter.cpp')
| -rw-r--r-- | utils/TableGen/SubtargetEmitter.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 4127b379b1..f115af1016 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -11,6 +11,8 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "subtarget-emitter" + #include "CodeGenTarget.h" #include "CodeGenSchedule.h" #include "llvm/ADT/StringExtras.h" @@ -769,6 +771,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(), SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) { + DEBUG(SCI->dump(&SchedModels)); + SCTab.resize(SCTab.size() + 1); MCSchedClassDesc &SCDesc = SCTab.back(); // SCDesc.Name is guarded by NDEBUG @@ -817,8 +821,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, } } else if (!SCI->InstRWs.empty()) { - assert(SCI->Writes.empty() && SCI->Reads.empty() && - "InstRW class should not have its own ReadWrites"); + // This class may have a default ReadWrite list which can be overriden by + // InstRW definitions. Record *RWDef = 0; for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end(); RWI != RWE; ++RWI) { |