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author | Sean Callanan <scallanan@apple.com> | 2011-03-15 01:23:15 +0000 |
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committer | Sean Callanan <scallanan@apple.com> | 2011-03-15 01:23:15 +0000 |
commit | a21e2eae3def2fe39caed861dcb73c76c715569b (patch) | |
tree | 33aec5978f0773fb9c409aa2ade730b0291700c4 /utils/TableGen/X86RecognizableInstr.h | |
parent | 4dbe200b2d3da0dfd1c788c9650b8b8075c241aa (diff) | |
download | llvm-a21e2eae3def2fe39caed861dcb73c76c715569b.tar.gz llvm-a21e2eae3def2fe39caed861dcb73c76c715569b.tar.bz2 llvm-a21e2eae3def2fe39caed861dcb73c76c715569b.tar.xz |
X86 table-generator and disassembler support for the AVX
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.h')
-rw-r--r-- | utils/TableGen/X86RecognizableInstr.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h index c043b909b4..c7ec18ca6d 100644 --- a/utils/TableGen/X86RecognizableInstr.h +++ b/utils/TableGen/X86RecognizableInstr.h @@ -52,8 +52,14 @@ private: bool HasOpSizePrefix; /// The hasREX_WPrefix field from the record bool HasREX_WPrefix; + /// The hasVEXPrefix field from the record + bool HasVEXPrefix; /// The hasVEX_4VPrefix field from the record bool HasVEX_4VPrefix; + /// The hasVEX_WPrefix field from the record + bool HasVEX_WPrefix; + /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set + bool HasVEX_LPrefix; /// The hasLockPrefix field from the record bool HasLockPrefix; /// The isCodeGenOnly filed from the record @@ -96,7 +102,7 @@ private: // error if it conflcits with any other FILTER_NORMAL // instruction }; - + /// filter - Determines whether the instruction should be decodable. Some /// instructions are pure intrinsics and use unencodable operands; many /// synthetic instructions are duplicates of other instructions; other @@ -106,6 +112,12 @@ private: /// /// @return - The degree of filtering to be applied (see filter_ret). filter_ret filter() const; + + /// hasFROperands - Returns true if any operand is a FR operand. + bool hasFROperands() const; + + /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand. + bool has256BitOperands() const; /// typeFromString - Translates an operand type from the string provided in /// the LLVM tables to an OperandType for use in the operand specifier. @@ -155,6 +167,8 @@ private: bool hasOpSizePrefix); static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, bool hasOpSizePrefix); + static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, + bool HasOpSizePrefix); /// handleOperand - Converts a single operand from the LLVM table format to /// the emitted table format, handling any duplicate operands it encounters |