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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-08-22 12:18:28 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-08-22 12:18:28 +0000 |
| commit | 1765e74c15c83db437018a3c9efabbeb4ce9cbde (patch) | |
| tree | 5bffe4d37b2c724573504c41789f04d8c4f420ea /utils/TableGen | |
| parent | 7ddda4704cdb24163591857e8d08614463cec335 (diff) | |
| download | llvm-1765e74c15c83db437018a3c9efabbeb4ce9cbde.tar.gz llvm-1765e74c15c83db437018a3c9efabbeb4ce9cbde.tar.bz2 llvm-1765e74c15c83db437018a3c9efabbeb4ce9cbde.tar.xz | |
AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 40 |
1 files changed, 23 insertions, 17 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 7962f9b983..d2675d7a62 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -818,17 +818,20 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM5r: case X86Local::MRM6r: case X86Local::MRM7r: - // Operand 1 is a register operand in the R/M field. - // Operand 2 (optional) is an immediate or relocation. - // Operand 3 (optional) is an immediate. - if (HasVEX_4VPrefix) - assert(numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnRFrm with VEX_4V"); - else - assert(numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnRFrm"); + { + // Operand 1 is a register operand in the R/M field. + // Operand 2 (optional) is an immediate or relocation. + // Operand 3 (optional) is an immediate. + unsigned kOp = (HasEVEX_K) ? 1:0; + unsigned Op4v = (HasVEX_4VPrefix) ? 1:0; + if (numPhysicalOperands > 3 + kOp + Op4v) + llvm_unreachable("Unexpected number of operands for MRMnr"); + } if (HasVEX_4VPrefix) HANDLE_OPERAND(vvvvRegister) + + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) HANDLE_OPTIONAL(rmRegister) HANDLE_OPTIONAL(relocation) HANDLE_OPTIONAL(immediate) @@ -841,16 +844,19 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM5m: case X86Local::MRM6m: case X86Local::MRM7m: - // Operand 1 is a memory operand (possibly SIB-extended) - // Operand 2 (optional) is an immediate or relocation. - if (HasVEX_4VPrefix) - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnMFrm"); - else - assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && - "Unexpected number of operands for MRMnMFrm"); + { + // Operand 1 is a memory operand (possibly SIB-extended) + // Operand 2 (optional) is an immediate or relocation. + unsigned kOp = (HasEVEX_K) ? 1:0; + unsigned Op4v = (HasVEX_4VPrefix) ? 1:0; + if (numPhysicalOperands < 1 + kOp + Op4v || + numPhysicalOperands > 2 + kOp + Op4v) + llvm_unreachable("Unexpected number of operands for MRMnm"); + } if (HasVEX_4VPrefix) HANDLE_OPERAND(vvvvRegister) + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) HANDLE_OPERAND(memory) HANDLE_OPTIONAL(relocation) break; |