Split out register class subclassing to a separate function and clean up

accordingly.  No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112008 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 33 insertions, 29 deletions

diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h
index 344f77f1fe..ccd3d222bb 100644
--- a/utils/TableGen/CodeGenRegisters.h
+++ b/utils/TableGen/CodeGenRegisters.h
@@ -19,6 +19,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include <string>
 #include <vector>
+#include <set>
 #include <cstdlib>
 
 namespace llvm {
@@ -55,6 +56,37 @@ namespace llvm {
       assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
       abort();
     }
+    
+    // Returns true if RC is a strict subclass.
+    // RC is a sub-class of this class if it is a valid replacement for any
+    // instruction operand where a register of this classis required. It must 
+    // satisfy these conditions:
+    //
+    // 1. All RC registers are also in this.
+    // 2. The RC spill size must not be smaller than our spill size.
+    // 3. RC spill alignment must be compatible with ours.
+    //
+    bool hasSubClass(const CodeGenRegisterClass *RC) const {
+
+      if (RC->Elements.size() > Elements.size() ||
+          (SpillAlignment && RC->SpillAlignment % SpillAlignment) ||
+          SpillSize > RC->SpillSize)
+        return false;
+
+      std::set<Record*> RegSet;
+      for (unsigned i = 0, e = Elements.size(); i != e; ++i) {
+        Record *Reg = Elements[i];
+        RegSet.insert(Reg);
+      }
+
+      for (unsigned i = 0, e = RC->Elements.size(); i != e; ++i) {
+        Record *Reg = RC->Elements[i];
+        if (!RegSet.count(Reg))
+          return false;
+      }
+
+      return true;
+    }
 
     CodeGenRegisterClass(Record *R);
   };
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index a3ca0bc552..6f06705243 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -119,16 +119,6 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
   OS << "} // End llvm namespace \n";
 }
 
-bool isSubRegisterClass(const CodeGenRegisterClass &RC,
-                        std::set<Record*> &RegSet) {
-  for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
-    Record *Reg = RC.Elements[i];
-    if (!RegSet.count(Reg))
-      return false;
-  }
-  return true;
-}
-
 static void addSuperReg(Record *R, Record *S,
                   std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
                   std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
@@ -498,12 +488,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
       // Give the register class a legal C name if it's anonymous.
       std::string Name = RC.TheDef->getName();
 
-      std::set<Record*> RegSet;
-      for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
-        Record *Reg = RC.Elements[i];
-        RegSet.insert(Reg);
-      }
-
       OS << "  // " << Name 
          << " Register Class sub-classes...\n"
          << "  static const TargetRegisterClass* const "
@@ -513,21 +497,9 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
       for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
         const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
 
-        // RC2 is a sub-class of RC if it is a valid replacement for any
-        // instruction operand where an RC register is required. It must satisfy
-        // these conditions:
-        //
-        // 1. All RC2 registers are also in RC.
-        // 2. The RC2 spill size must not be smaller that the RC spill size.
-        // 3. RC2 spill alignment must be compatible with RC.
-        //
         // Sub-classes are used to determine if a virtual register can be used
         // as an instruction operand, or if it must be copied first.
-
-        if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
-            (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
-            RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
-          continue;
+        if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
       
         if (!Empty) OS << ", ";
         OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";