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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-10 12:47:23 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-10 12:47:23 +0000 |
| commit | 8316a97e024de3b335386922a6c3b6e1a7b197f5 (patch) | |
| tree | 01da8a9ee21fe5d95ce979e7103a36bab6988a09 /utils | |
| parent | 2093e88d67a92721fe070b93dda01a6946079f2f (diff) | |
| download | llvm-8316a97e024de3b335386922a6c3b6e1a7b197f5.tar.gz llvm-8316a97e024de3b335386922a6c3b6e1a7b197f5.tar.bz2 llvm-8316a97e024de3b335386922a6c3b6e1a7b197f5.tar.xz | |
Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210527 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/AsmWriterEmitter.cpp | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 2741d8f4ad..2bd9f80540 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -832,6 +832,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { unsigned MIOpNum = 0; for (unsigned i = 0, e = LastOpNo; i != e; ++i) { + std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; + const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; switch (RO.Kind) { @@ -858,9 +860,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { if (Rec->isSubClassOf("RegisterOperand")) Rec = Rec->getValueAsDef("RegClass"); if (Rec->isSubClassOf("RegisterClass")) { - Cond = std::string("MI->getOperand(") + llvm::utostr(MIOpNum) + - ").isReg()"; - IAP->addCond(Cond); + IAP->addCond(Op + ".isReg()"); if (!IAP->isOpMapped(ROName)) { IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); @@ -869,12 +869,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { R = R->getValueAsDef("RegClass"); Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + R->getName() + "RegClassID)" - ".contains(MI->getOperand(" + - llvm::utostr(MIOpNum) + ").getReg())"; + ".contains(" + Op + ".getReg())"; IAP->addCond(Cond); } else { - Cond = std::string("MI->getOperand(") + - llvm::utostr(MIOpNum) + ").getReg() == MI->getOperand(" + + Cond = Op + ".getReg() == MI->getOperand(" + llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; IAP->addCond(Cond); } @@ -887,8 +885,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { break; } case CodeGenInstAlias::ResultOperand::K_Imm: { - std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; - // Just because the alias has an immediate result, doesn't mean the // MCInst will. An MCExpr could be present, for example. IAP->addCond(Op + ".isImm()"); @@ -906,8 +902,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { break; } - Cond = std::string("MI->getOperand(") + - llvm::utostr(MIOpNum) + ").getReg() == " + Target.getName() + + Cond = Op + ".getReg() == " + Target.getName() + "::" + CGA->ResultOperands[i].getRegister()->getName(); IAP->addCond(Cond); break; |