[x86] Fix disassembly of MOV16ao16 et al.

The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 10 insertions, 6 deletions

diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index 0ccfac7855..f9c3e1ab2f 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -94,11 +94,8 @@ static inline bool inheritsFrom(InstructionContext child,
            inheritsFrom(child, IC_64BIT_XD)     ||
            inheritsFrom(child, IC_64BIT_XS));
   case IC_OPSIZE:
-    return (inheritsFrom(child, IC_64BIT_OPSIZE) ||
-            inheritsFrom(child, IC_OPSIZE_ADSIZE));
+    return inheritsFrom(child, IC_64BIT_OPSIZE);
   case IC_ADSIZE:
-    return inheritsFrom(child, IC_OPSIZE_ADSIZE);
-  case IC_OPSIZE_ADSIZE:
   case IC_64BIT_ADSIZE:
     return false;
   case IC_XD:
@@ -803,6 +800,15 @@ void DisassemblerTables::setTableFields(ModRMDecision     &decision,
         if(newInfo.filtered)
           continue; // filtered instructions get lowest priority
 
+        // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
+        // presence of the AdSize prefix. However, the disassembler doesn't
+        // care about that difference in the instruction definition; it
+        // handles 16-bit vs. 32-bit addressing for itself based purely
+        // on the 0x67 prefix and the CPU mode. So there's no need to
+        // disambiguate between them; just let them conflict/coexist.
+        if (previousInfo.name + "_16" == newInfo.name)
+          continue;
+
         if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
                                            newInfo.name == "XCHG32ar" ||
                                            newInfo.name == "XCHG32ar64" ||
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 019610e147..c09abefeef 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -468,8 +468,6 @@ InstructionContext RecognizableInstr::insnContext() const {
     else if (HasOpSizePrefix &&
              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
       insnContext = IC_XS_OPSIZE;
-    else if (HasOpSizePrefix && HasAdSizePrefix)
-      insnContext = IC_OPSIZE_ADSIZE;
     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
              Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
       insnContext = IC_OPSIZE;