diff options
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 21 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonPeephole.cpp | 19 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/combine_ir.ll | 7 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/union-1.ll | 23 |
4 files changed, 64 insertions, 6 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 3db857d27f..2a4b17b173 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2550,6 +2550,27 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), IntRegs:$srcLow))>; +let AddedComplexity = 100 in +def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), + (i32 32))), + (i64 (zextloadi32 (i32 (add IntRegs:$src2, + s11_2ExtPred:$offset2)))))), + (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), + (LDriw_indexed IntRegs:$src2, + s11_2ExtPred:$offset2)))>; + +def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), + (i32 32))), + (i64 (zextloadi32 ADDRriS11_2:$srcLow)))), + (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), + (LDriw ADDRriS11_2:$srcLow)))>; + +def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), + (i32 32))), + (i64 (zext (i32 IntRegs:$srcLow))))), + (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), + IntRegs:$srcLow))>; + // Any extended 64-bit load. // anyext i32 -> i64 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)), diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index 576f1d7d07..6c4eb7e668 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -73,6 +73,10 @@ static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of Sign/Zero Extends")); +static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Optimization of extensions to i64.")); + namespace { struct HexagonPeephole : public MachineFunctionPass { const HexagonInstrInfo *QII; @@ -142,6 +146,21 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { } } + // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169) + // %vreg170:DoublRegs, %vreg169:IntRegs + if (!DisableOptExtTo64 && + MI->getOpcode () == Hexagon::COMBINE_Ir_V4) { + assert (MI->getNumOperands() == 3); + MachineOperand &Dst = MI->getOperand(0); + MachineOperand &Src1 = MI->getOperand(1); + MachineOperand &Src2 = MI->getOperand(2); + if (Src1.getImm() != 0) + continue; + unsigned DstReg = Dst.getReg(); + unsigned SrcReg = Src2.getReg(); + PeepholeMap[DstReg] = SrcReg; + } + // Look for this sequence below // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32 // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg. diff --git a/test/CodeGen/Hexagon/combine_ir.ll b/test/CodeGen/Hexagon/combine_ir.ll index 921ce9928e..8b99ef7155 100644 --- a/test/CodeGen/Hexagon/combine_ir.ll +++ b/test/CodeGen/Hexagon/combine_ir.ll @@ -6,12 +6,7 @@ define void @word(i32* nocapture %a) nounwind { entry: %0 = load i32* %a, align 4, !tbaa !0 %1 = zext i32 %0 to i64 - %add.ptr = getelementptr inbounds i32* %a, i32 1 - %2 = load i32* %add.ptr, align 4, !tbaa !0 - %3 = zext i32 %2 to i64 - %4 = shl nuw i64 %3, 32 - %ins = or i64 %4, %1 - tail call void @bar(i64 %ins) nounwind + tail call void @bar(i64 %1) nounwind ret void } diff --git a/test/CodeGen/Hexagon/union-1.ll b/test/CodeGen/Hexagon/union-1.ll new file mode 100644 index 0000000000..7c6da744ec --- /dev/null +++ b/test/CodeGen/Hexagon/union-1.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; CHECK: word +; CHECK-NOT: combine(#0 +; CHECK: jump bar + +define void @word(i32* nocapture %a) nounwind { +entry: + %0 = load i32* %a, align 4, !tbaa !0 + %1 = zext i32 %0 to i64 + %add.ptr = getelementptr inbounds i32* %a, i32 1 + %2 = load i32* %add.ptr, align 4, !tbaa !0 + %3 = zext i32 %2 to i64 + %4 = shl nuw i64 %3, 32 + %ins = or i64 %4, %1 + tail call void @bar(i64 %ins) nounwind + ret void +} + +declare void @bar(i64) + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} |