diff options
| -rw-r--r-- | docs/CodeGenerator.html | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 12 | ||||
| -rw-r--r-- | test/CodeGen/X86/movfs.ll | 8 |
4 files changed, 31 insertions, 4 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index b4edbd7356..e620c1782e 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1844,11 +1844,13 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm segment. LLVM address space 0 is the default address space, which includes the stack, and any unqualified memory accesses in a program. Address spaces 1-255 are currently reserved for user-defined code. The GS-segment is - represented by address space 256. Other x86 segments have yet to be - allocated address space numbers.</p> + represented by address space 256, while the FS-segment is represented by + address space 257. Other x86 segments have yet to be allocated address space + numbers.</p> -<p>Some operating systems use the GS-segment to implement TLS, so care should be - taken when reading and writing to address space 256 on these platforms.</p> +<p>Some operating systems use the FS/GS-segment to implement TLS, so care + should be taken when reading and writing to address space 256/257 on these + platforms.</p> </div> diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 715eb006e5..77847e474d 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1326,6 +1326,11 @@ def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "movq\t%gs:$src, $dst", [(set GR64:$dst, (gsload addr:$src))]>, SegGS; +let AddedComplexity = 5 in +def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "movq\t%fs:$src, $dst", + [(set GR64:$dst, (fsload addr:$src))]>, SegFS; + //===----------------------------------------------------------------------===// // Atomic Instructions //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 33e0a3d67d..0d3b6857e6 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -345,6 +345,13 @@ def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return false; }]>; +def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) + if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) + return PT->getAddressSpace() == 257; + return false; +}]>; + def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) @@ -3004,6 +3011,11 @@ def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "movl\t%gs:$src, $dst", [(set GR32:$dst, (gsload addr:$src))]>, SegGS; +let AddedComplexity = 5 in +def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "movl\t%fs:$src, $dst", + [(set GR32:$dst, (fsload addr:$src))]>, SegFS; + //===----------------------------------------------------------------------===// // DWARF Pseudo Instructions // diff --git a/test/CodeGen/X86/movfs.ll b/test/CodeGen/X86/movfs.ll new file mode 100644 index 0000000000..af102d4956 --- /dev/null +++ b/test/CodeGen/X86/movfs.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep fs + +define i32 @foo() nounwind readonly { +entry: + %tmp = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1] + %tmp1 = load i32* %tmp ; <i32> [#uses=1] + ret i32 %tmp1 +} |