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-rw-r--r--lib/Target/X86/X86InstrControl.td4
-rw-r--r--lib/Target/X86/X86InstrInfo.td3
-rw-r--r--test/MC/X86/x86-64.s3
3 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td
index 5f1f2dfef1..ee20ebca06 100644
--- a/lib/Target/X86/X86InstrControl.td
+++ b/lib/Target/X86/X86InstrControl.td
@@ -27,8 +27,8 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"retw\t$amt",
[(X86retflag timm:$amt)]>, OpSize;
- def LRET : I <0xCB, RawFrm, (outs), (ins),
- "lret", []>;
+ def LRETL : I <0xCB, RawFrm, (outs), (ins),
+ "lretl", []>;
def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
"lretq", []>;
def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 148264d4dc..0a60eb7b91 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1264,6 +1264,9 @@ def : MnemonicAlias<"cdq", "cltd">;
def : MnemonicAlias<"cwde", "cwtl">;
def : MnemonicAlias<"cdqe", "cltq">;
+// lret maps to lretl, it is not ambiguous with lretq.
+def : MnemonicAlias<"lret", "lretl">;
+
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index 66074f0211..b8b093c19b 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -771,7 +771,8 @@ iretq
// PR8592
lretq // CHECK: lretq # encoding: [0x48,0xcb]
-lret // CHECK: lret # encoding: [0xcb]
+lretl // CHECK: lretl # encoding: [0xcb]
+lret // CHECK: lretl # encoding: [0xcb]
// rdar://8403907
sysret