diff options
-rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 21 | ||||
-rw-r--r-- | test/CodeGen/X86/fast-isel-fneg.ll | 6 |
2 files changed, 7 insertions, 20 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 8550ea9813..f0c7086184 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -615,25 +615,12 @@ FastISel::SelectFNeg(User *I) { unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); if (OpReg == 0) return false; - // Bitcast the value to integer, twiddle the sign bit with xor, - // and then bitcast it back to floating-point. + // Twiddle the sign bit with xor. EVT VT = TLI.getValueType(I->getType()); if (VT.getSizeInBits() > 64) return false; - EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); - - unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), - ISD::BIT_CONVERT, OpReg); - if (IntReg == 0) - return false; - - unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, - UINT64_C(1) << (VT.getSizeInBits()-1), - IntVT.getSimpleVT()); - if (IntResultReg == 0) - return false; - - unsigned ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), - ISD::BIT_CONVERT, IntResultReg); + unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg, + UINT64_C(1) << (VT.getSizeInBits()-1), + VT.getSimpleVT()); if (ResultReg == 0) return false; diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll index 70191bdfdf..15d4772927 100644 --- a/test/CodeGen/X86/fast-isel-fneg.ll +++ b/test/CodeGen/X86/fast-isel-fneg.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s +; RUN: llc < %s -fast-isel -march=x86-64 | FileCheck %s ; CHECK: doo: -; CHECK: xor +; CHECK: xorpd define double @doo(double %x) nounwind { %y = fsub double -0.0, %x ret double %y } ; CHECK: foo: -; CHECK: xor +; CHECK: xorps define float @foo(float %x) nounwind { %y = fsub float -0.0, %x ret float %y |