diff options
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 18 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrBuilder.h | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/fast-isel-gv.ll | 24 |
3 files changed, 42 insertions, 6 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 8a21b35c13..ea29f73a06 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -457,20 +457,30 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) { AM.GV = 0; return true; } - // Issue load from stub if necessary. + + // Issue load from stub. unsigned Opc = 0; const TargetRegisterClass *RC = NULL; + X86AddressMode StubAM; + StubAM.Base.Reg = AM.Base.Reg; + StubAM.GV = AM.GV; + if (TLI.getPointerTy() == MVT::i32) { Opc = X86::MOV32rm; RC = X86::GR32RegisterClass; + + if (Subtarget->isPICStyleGOT() && + TM.getRelocationModel() == Reloc::PIC_) + StubAM.GVOpFlags = X86II::MO_GOT; + } else { Opc = X86::MOV64rm; RC = X86::GR64RegisterClass; + + if (TM.getRelocationModel() != Reloc::Static) + StubAM.GVOpFlags = X86II::MO_GOTPCREL; } - X86AddressMode StubAM; - StubAM.Base.Reg = AM.Base.Reg; - StubAM.GV = AM.GV; unsigned ResultReg = createResultReg(RC); addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM); diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h index b50dd65a29..6359542819 100644 --- a/lib/Target/X86/X86InstrBuilder.h +++ b/lib/Target/X86/X86InstrBuilder.h @@ -49,8 +49,10 @@ struct X86AddressMode { unsigned IndexReg; unsigned Disp; GlobalValue *GV; + unsigned GVOpFlags; - X86AddressMode() : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0) { + X86AddressMode() + : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) { Base.Reg = 0; } }; @@ -113,7 +115,7 @@ inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB, assert (0); MIB.addImm(AM.Scale).addReg(AM.IndexReg); if (AM.GV) - return MIB.addGlobalAddress(AM.GV, AM.Disp); + return MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); else return MIB.addImm(AM.Disp); } diff --git a/test/CodeGen/X86/fast-isel-gv.ll b/test/CodeGen/X86/fast-isel-gv.ll new file mode 100644 index 0000000000..7a4b94d1b9 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-gv.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -fast-isel | grep {_kill@GOTPCREL} +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" +@f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1] + +declare signext i8 @kill(...) + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %1 = load i8 (...)** @f, align 8 ; <i8 (...)*> [#uses=1] + %2 = icmp ne i8 (...)* %1, @kill ; <i1> [#uses=1] + %3 = zext i1 %2 to i32 ; <i32> [#uses=1] + store i32 %3, i32* %0, align 4 + %4 = load i32* %0, align 4 ; <i32> [#uses=1] + store i32 %4, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval1 +} |