diff options
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 8 | ||||
| -rw-r--r-- | lib/CodeGen/PeepholeOptimizer.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 38 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/jump_sign.ll | 11 |
5 files changed, 61 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index d3c5e20766..896c152f93 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -640,6 +640,14 @@ public: return false; } + /// OptimizeSubInstr - See if the SUB instruction can be converted into + /// something more efficient E.g., on X86, we can replace SUB with CMP + /// if the actual result of SUB is not used. + virtual bool OptimizeSubInstr(MachineInstr *SubInstr, + const MachineRegisterInfo *MRI) const { + return false; + } + /// FoldImmediate - 'Reg' is known to be defined by a move immediate /// instruction, try to fold the immediate into the use instruction. virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index 81cf9011d1..d7d112f1d9 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -472,6 +472,7 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { if (SeenMoveImm) Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs); } + Changed |= TII->OptimizeSubInstr(MI, MRI); First = false; PMII = MII; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 7254ddf56c..2dd5c12c65 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2709,6 +2709,44 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, NewMIs.push_back(MIB); } +bool X86InstrInfo:: +OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const { + // If destination is a memory operand, do not perform this optimization. + if ((SubInstr->getOpcode() != X86::SUB64rr) && + (SubInstr->getOpcode() != X86::SUB32rr) && + (SubInstr->getOpcode() != X86::SUB16rr) && + (SubInstr->getOpcode() != X86::SUB8rr) && + (SubInstr->getOpcode() != X86::SUB64ri32) && + (SubInstr->getOpcode() != X86::SUB64ri8) && + (SubInstr->getOpcode() != X86::SUB32ri) && + (SubInstr->getOpcode() != X86::SUB32ri8) && + (SubInstr->getOpcode() != X86::SUB16ri) && + (SubInstr->getOpcode() != X86::SUB16ri8) && + (SubInstr->getOpcode() != X86::SUB8ri)) + return false; + unsigned DestReg = SubInstr->getOperand(0).getReg(); + if (MRI->use_begin(DestReg) != MRI->use_end()) + return false; + + // There is no use of the destination register, we can replace SUB with CMP. + switch (SubInstr->getOpcode()) { + default: break; + case X86::SUB64rr: SubInstr->setDesc(get(X86::CMP64rr)); break; + case X86::SUB32rr: SubInstr->setDesc(get(X86::CMP32rr)); break; + case X86::SUB16rr: SubInstr->setDesc(get(X86::CMP16rr)); break; + case X86::SUB8rr: SubInstr->setDesc(get(X86::CMP8rr)); break; + case X86::SUB64ri32: SubInstr->setDesc(get(X86::CMP64ri32)); break; + case X86::SUB64ri8: SubInstr->setDesc(get(X86::CMP64ri8)); break; + case X86::SUB32ri: SubInstr->setDesc(get(X86::CMP32ri)); break; + case X86::SUB32ri8: SubInstr->setDesc(get(X86::CMP32ri8)); break; + case X86::SUB16ri: SubInstr->setDesc(get(X86::CMP16ri)); break; + case X86::SUB16ri8: SubInstr->setDesc(get(X86::CMP16ri8)); break; + case X86::SUB8ri: SubInstr->setDesc(get(X86::CMP8ri)); break; + } + SubInstr->RemoveOperand(0); + return true; +} + /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr /// instruction with two undef reads of the register being defined. This is /// used for mapping: diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 856f3be57c..9c4d46522c 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -365,6 +365,9 @@ public: const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const; + virtual bool OptimizeSubInstr(MachineInstr *SubInstr, + const MachineRegisterInfo *MRI) const; + private: MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, MachineFunction::iterator &MFI, diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll index 94cbe5d193..cf5408e071 100644 --- a/test/CodeGen/X86/jump_sign.ll +++ b/test/CodeGen/X86/jump_sign.ll @@ -83,3 +83,14 @@ entry: %cond = select i1 %cmp, i32 %sub, i32 0 ret i32 %cond } +; rdar://11540023 +define i64 @n(i64 %x, i64 %y) nounwind { +entry: +; CHECK: n: +; CHECK-NOT: sub +; CHECK: cmp + %sub = sub nsw i64 %x, %y + %cmp = icmp slt i64 %sub, 0 + %y.x = select i1 %cmp, i64 %y, i64 %x + ret i64 %y.x +} |