diff options
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 18 | ||||
| -rw-r--r-- | test/CodeGen/R600/add_i64.ll | 21 |
2 files changed, 36 insertions, 3 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index a5d4e1ab06..7f23ecf91f 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -417,6 +417,7 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { MachineOperand &MO = MI->getOperand(OpIdx); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; + // XXX - This shouldn't be VSrc const TargetRegisterClass *RC = RI.getRegClass(RCID); unsigned Opcode = AMDGPU::V_MOV_B32_e32; if (MO.isReg()) { @@ -442,8 +443,24 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { // Legalize VOP2 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) { + MachineOperand &Src0 = MI->getOperand(Src0Idx); MachineOperand &Src1 = MI->getOperand(Src1Idx); + // If the instruction implicitly reads VCC, we can't have any SGPR operands, + // so move any. + bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI); + if (ReadsVCC && Src0.isReg() && + RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) { + legalizeOpWithMove(MI, Src0Idx); + return; + } + + if (ReadsVCC && Src1.isReg() && + RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { + legalizeOpWithMove(MI, Src1Idx); + return; + } + // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must // be the first operand, and there can only be one. if (Src1.isImm() || Src1.isFPImm() || @@ -456,6 +473,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { } } + // XXX - Do any VOP3 instructions read VCC? // Legalize VOP3 if (isVOP3(MI->getOpcode())) { int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx}; diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll index 1f846b4ed3..c5c2a11e62 100644 --- a/test/CodeGen/R600/add_i64.ll +++ b/test/CodeGen/R600/add_i64.ll @@ -18,13 +18,28 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ret void } -; SI-LABEL: @test_i64_sreg: -define void @test_i64_sreg(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) { - %result = add i64 %a, %b +; SI-LABEL: @one_sgpr: +define void @one_sgpr(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { + %foo = load i64 addrspace(1)* %in, align 8 + %result = add i64 %foo, %a store i64 %result, i64 addrspace(1)* %out ret void } +; FIXME: This case is broken +; +; Swap the arguments. Check that the SGPR -> VGPR copy works with the +; SGPR as other operand. +; +; XXXSI-LABEL: @one_sgpr_reversed: +; define void @one_sgpr_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { +; %foo = load i64 addrspace(1)* %in, align 8 +; %result = add i64 %a, %foo +; store i64 %result, i64 addrspace(1)* %out +; ret void +; } + + ; SI-LABEL: @test_v2i64_sreg: define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { %result = add <2 x i64> %a, %b |