diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 | ||||
| -rw-r--r-- | test/CodeGen/X86/neg-shl-add.ll | 17 |
2 files changed, 37 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7fe908c730..8883064df9 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1088,6 +1088,26 @@ SDValue DAGCombiner::visitADD(SDNode *N) { if (Result.getNode()) return Result; } + // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) + if (N1.getOpcode() == ISD::SHL && + N1.getOperand(0).getOpcode() == ISD::SUB) + if (ConstantSDNode *C = + dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) + if (C->getAPIntValue() == 0) + return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, + DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, + N1.getOperand(0).getOperand(1), + N1.getOperand(1))); + if (N0.getOpcode() == ISD::SHL && + N0.getOperand(0).getOpcode() == ISD::SUB) + if (ConstantSDNode *C = + dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) + if (C->getAPIntValue() == 0) + return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, + DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, + N0.getOperand(0).getOperand(1), + N0.getOperand(1))); + return SDValue(); } diff --git a/test/CodeGen/X86/neg-shl-add.ll b/test/CodeGen/X86/neg-shl-add.ll new file mode 100644 index 0000000000..7aebc383dd --- /dev/null +++ b/test/CodeGen/X86/neg-shl-add.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=x86-64 < %s | not grep negq + +; These sequences don't need neg instructions; they can be done with +; a single shift and sub each. + +define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind { + %a = sub i64 0, %y + %b = shl i64 %a, %n + %c = add i64 %b, %x + ret i64 %c +} +define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind { + %a = sub i64 0, %y + %b = shl i64 %a, %n + %c = add i64 %x, %b + ret i64 %c +} |