diff options
| -rw-r--r-- | lib/CodeGen/MachineScheduler.cpp | 26 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-copy.ll | 18 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-matmul.ll | 9 |
3 files changed, 34 insertions, 19 deletions
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index d9850d32f0..9600cb6943 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -1594,6 +1594,12 @@ private: SchedBoundary Top; SchedBoundary Bot; + // Allow the driver to force top-down or bottom-up scheduling. If neither is + // true, the scheduler runs in both directions and converges. For generic + // targets, we default to bottom-up, because it's simpler and more + // compile-time optimizations have been implemented in that direction. + bool OnlyBottomUp; + bool OnlyTopDown; public: /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both) enum { @@ -1604,7 +1610,8 @@ public: ConvergingScheduler(const MachineSchedContext *C): Context(C), DAG(0), SchedModel(0), TRI(0), - Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} + Top(TopQID, "TopQ"), Bot(BotQID, "BotQ"), + OnlyBottomUp(true), OnlyTopDown(false) {} virtual bool shouldTrackPressure(unsigned NumRegionInstrs); @@ -1709,6 +1716,19 @@ void ConvergingScheduler::initialize(ScheduleDAGMI *dag) { } assert((!ForceTopDown || !ForceBottomUp) && "-misched-topdown incompatible with -misched-bottomup"); + + // Check -misched-topdown/bottomup can force or unforce scheduling direction. + // e.g. -misched-bottomup=false allows scheduling in both directions. + if (ForceBottomUp.getNumOccurrences() > 0) { + OnlyBottomUp = ForceBottomUp; + if (OnlyBottomUp) + OnlyTopDown = false; + } + if (ForceTopDown.getNumOccurrences() > 0) { + OnlyTopDown = ForceTopDown; + if (OnlyTopDown) + OnlyBottomUp = false; + } } void ConvergingScheduler::releaseTopNode(SUnit *SU) { @@ -2674,7 +2694,7 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) { } SUnit *SU; do { - if (ForceTopDown) { + if (OnlyTopDown) { SU = Top.pickOnlyChoice(); if (!SU) { CandPolicy NoPolicy; @@ -2686,7 +2706,7 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) { } IsTopNode = true; } - else if (ForceBottomUp) { + else if (OnlyBottomUp) { SU = Bot.pickOnlyChoice(); if (!SU) { CandPolicy NoPolicy; diff --git a/test/CodeGen/X86/misched-copy.ll b/test/CodeGen/X86/misched-copy.ll index 5970dcd31f..4485b8a244 100644 --- a/test/CodeGen/X86/misched-copy.ll +++ b/test/CodeGen/X86/misched-copy.ll @@ -1,12 +1,4 @@ ; REQUIRES: asserts -; -; FIXME: The following line is a hack to remove any stray files which might have -; been left dangling around by this test. It can be removed once the various -; bots have cycled past this commit. -; -; RUN: rm -f misched-copy.s %S/misched-copy.s -; -; ; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s ; ; Test scheduling of copy instructions. @@ -16,11 +8,11 @@ ; MUL_HiLo PhysReg use copies should be just above the mul. ; MUL_HiLo PhysReg def copies should be just below the mul. ; -; CHECK: *** Final schedule for BB#1 *** -; CHECK-NEXT: %EAX<def> = COPY -; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; -; CHECK-NEXT: COPY %E{{[AD]}}X; -; CHECK-NEXT: COPY %E{{[AD]}}X; +; CHECK: *** Final schedule for BB#1 *** +; CHECK: %EAX<def> = COPY +; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; +; CHECK-NEXT: COPY %E{{[AD]}}X +; CHECK-NEXT: COPY %E{{[AD]}}X ; CHECK: DIVSSrm define i64 @mulhoist(i32 %a, i32 %b) #0 { entry: diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll index fe78e70f05..5454b7cf78 100644 --- a/test/CodeGen/X86/misched-matmul.ll +++ b/test/CodeGen/X86/misched-matmul.ll @@ -3,11 +3,14 @@ ; ; Verify that register pressure heuristics are working in MachineScheduler. ; -; When we enable subtree scheduling heuristics on X86, we may need a -; flag to disable it for this test case. +; We can further reduce spills in this case with a global register +; pressure heuristic, like sethi-ullman numbers or biasing toward +; scheduled subtrees. However, these heuristics are marginally +; beneficial on x86_64 and exacerbate register pressure in other +; more complex cases. ; ; CHECK: @wrap_mul4 -; CHECK: 22 regalloc - Number of spills inserted +; CHECK: 23 regalloc - Number of spills inserted define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 { entry: |