diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 49 | ||||
| -rw-r--r-- | test/CodeGen/X86/2012-08-16-setcc.ll | 45 | ||||
| -rw-r--r-- | test/CodeGen/X86/fold-load.ll | 4 |
3 files changed, 8 insertions, 90 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 79e99db34b..c77355f917 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8283,18 +8283,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, unsigned Opcode = 0; unsigned NumOperands = 0; - - // Truncate operations may prevent the merge of the SETCC instruction - // and the arithmetic intruction before it. Attempt to truncate the operands - // of the arithmetic instruction and use a reduced bit-width instruction. - bool NeedTruncation = false; - unsigned InOpcode = Op.getNode()->getOpcode(); - if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { - NeedTruncation = true; - InOpcode = Op->getOperand(0)->getOpcode(); - } - - switch (InOpcode) { + switch (Op.getNode()->getOpcode()) { case ISD::ADD: // Due to an isel shortcoming, be conservative if this add is likely to be // selected as part of a load-modify-store instruction. When the root node @@ -8350,7 +8339,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && - !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) { + (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { NonFlagUse = true; break; } @@ -8371,9 +8360,11 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, goto default_case; // Otherwise use a regular EFLAGS-setting instruction. - switch (InOpcode) { + switch (Op.getNode()->getOpcode()) { default: llvm_unreachable("unexpected operator!"); - case ISD::SUB: Opcode = X86ISD::SUB; break; + case ISD::SUB: + Opcode = X86ISD::SUB; + break; case ISD::OR: Opcode = X86ISD::OR; break; case ISD::XOR: Opcode = X86ISD::XOR; break; case ISD::AND: Opcode = X86ISD::AND; break; @@ -8394,34 +8385,6 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, break; } - if (NeedTruncation) { - SDValue WideVal = Op->getOperand(0); - EVT VT = Op.getValueType(); - EVT WideVT = WideVal.getValueType(); - unsigned ConvertedOp = 0; - - // Use a target machine opcode to prevent further DAGCombine - // optimizations that may separate the arithmetic operations from the - // setcc node. - switch (WideVal.getOpcode()) { - default: break; - case ISD::ADD: ConvertedOp = X86ISD::ADD; break; - case ISD::SUB: ConvertedOp = X86ISD::SUB; break; - case ISD::AND: ConvertedOp = X86ISD::AND; break; - case ISD::OR: ConvertedOp = X86ISD::OR; break; - case ISD::XOR: ConvertedOp = X86ISD::XOR; break; - } - - if (ConvertedOp && WideVal.hasOneUse()) { - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { - SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0)); - SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1)); - Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1); - } - } - } - if (Opcode == 0) // Emit a CMP with 0, which is the TEST pattern. return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, diff --git a/test/CodeGen/X86/2012-08-16-setcc.ll b/test/CodeGen/X86/2012-08-16-setcc.ll deleted file mode 100644 index ed511567c3..0000000000 --- a/test/CodeGen/X86/2012-08-16-setcc.ll +++ /dev/null @@ -1,45 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s - -; rdar://12081007 - -; CHECK: and_1: -; CHECK: andb -; CHECK-NEXT: cmovnel -; CHECK: ret -define i32 @and_1(i8 zeroext %a, i8 zeroext %b, i32 %x) { - %1 = and i8 %b, %a - %2 = icmp ne i8 %1, 0 - %3 = select i1 %2, i32 %x, i32 0 - ret i32 %3 -} - -; CHECK: and_2: -; CHECK: andb -; CHECK-NEXT: setne -; CHECK: ret -define zeroext i1 @and_2(i8 zeroext %a, i8 zeroext %b) { - %1 = and i8 %b, %a - %2 = icmp ne i8 %1, 0 - ret i1 %2 -} - -; CHECK: xor_1: -; CHECK: xorb -; CHECK-NEXT: cmovnel -; CHECK: ret -define i32 @xor_1(i8 zeroext %a, i8 zeroext %b, i32 %x) { - %1 = xor i8 %b, %a - %2 = icmp ne i8 %1, 0 - %3 = select i1 %2, i32 %x, i32 0 - ret i32 %3 -} - -; CHECK: xor_2: -; CHECK: xorb -; CHECK-NEXT: setne -; CHECK: ret -define zeroext i1 @xor_2(i8 zeroext %a, i8 zeroext %b) { - %1 = xor i8 %b, %a - %2 = icmp ne i8 %1, 0 - ret i1 %2 -} diff --git a/test/CodeGen/X86/fold-load.ll b/test/CodeGen/X86/fold-load.ll index d8366654c0..c961f7576f 100644 --- a/test/CodeGen/X86/fold-load.ll +++ b/test/CodeGen/X86/fold-load.ll @@ -57,13 +57,13 @@ entry: %0 = load i32* %P, align 4 %1 = load i32* %Q, align 4 %2 = xor i32 %0, %1 - %3 = and i32 %2, 89947 + %3 = and i32 %2, 65535 %4 = icmp eq i32 %3, 0 br i1 %4, label %exit, label %land.end exit: %shr.i.i19 = xor i32 %1, %0 - %5 = and i32 %shr.i.i19, 3456789123 + %5 = and i32 %shr.i.i19, 2147418112 %6 = icmp eq i32 %5, 0 br label %land.end |