diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 27 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 44 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/icmp32.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/cmp.ll | 10 |
4 files changed, 34 insertions, 53 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index d439a6f869..14f0ef518f 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2342,6 +2342,33 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); } } + } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || + Cond == ISD::SETULE || Cond == ISD::SETUGT) { + bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); + // X < 0x100000000 -> (X >> 32) < 1 + // X >= 0x100000000 -> (X >> 32) >= 1 + // X <= 0x0ffffffff -> (X >> 32) < 1 + // X > 0x0ffffffff -> (X >> 32) >= 1 + unsigned ShiftBits; + APInt NewC = C1; + ISD::CondCode NewCond = Cond; + if (AdjOne) { + ShiftBits = C1.countTrailingOnes(); + NewC = NewC + 1; + NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; + } else { + ShiftBits = C1.countTrailingZeros(); + } + NewC = NewC.lshr(ShiftBits); + if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { + EVT ShiftTy = DCI.isBeforeLegalize() ? + getPointerTy() : getShiftAmountTy(N0.getValueType()); + EVT CmpTy = N0.getValueType(); + SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, + DAG.getConstant(ShiftBits, ShiftTy)); + SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); + return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); + } } } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 347f1977e7..4f642ec542 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3059,50 +3059,6 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, RHS = DAG.getConstant(0, RHS.getValueType()); return X86::COND_LE; } - if (SetCCOpcode == ISD::SETULT || SetCCOpcode == ISD::SETUGE) { - unsigned TrailZeros = RHSC->getAPIntValue().countTrailingZeros(); - if (TrailZeros >= 32) { - // The constant doesn't fit in cmp immediate field. Right shift LHS by - // the # of trailing zeros and truncate it to 32-bit. Then compare - // against shifted RHS. - assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!"); - DebugLoc dl = LHS.getDebugLoc(); - LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, - DAG.getNode(ISD::SRL, dl, MVT::i64, LHS, - DAG.getConstant(TrailZeros, MVT::i8))); - uint64_t C = RHSC->getZExtValue() >> TrailZeros; - - if (SetCCOpcode == ISD::SETULT) { - // X < 0x300000000 -> (X >> 32) < 3 - // X < 0x100000000 -> (X >> 32) == 0 - // X < 0x200000000 -> (X >> 33) == 0 - if (C == 1) { - RHS = DAG.getConstant(0, MVT::i32); - return X86::COND_E; - } - RHS = DAG.getConstant(C, MVT::i32); - return X86::COND_B; - } else /* SetCCOpcode == ISD::SETUGE */ { - // X >= 0x100000000 -> (X >> 32) >= 1 - RHS = DAG.getConstant(C, MVT::i32); - return X86::COND_AE; - } - } - } - if (SetCCOpcode == ISD::SETUGT) { - unsigned TrailOnes = RHSC->getAPIntValue().countTrailingOnes(); - if (TrailOnes >= 32 && !RHSC->isAllOnesValue()) { - assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!"); - DebugLoc dl = LHS.getDebugLoc(); - LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, - DAG.getNode(ISD::SRL, dl, MVT::i64, LHS, - DAG.getConstant(TrailOnes, MVT::i8))); - uint64_t C = (RHSC->getZExtValue()+1) >> TrailOnes; - // X > 0x0ffffffff -> (X >> 32) >= 1 - RHS = DAG.getConstant(C, MVT::i32); - return X86::COND_AE; - } - } } switch (SetCCOpcode) { diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll index ea912847e8..1794f4cd7b 100644 --- a/test/CodeGen/CellSPU/icmp32.ll +++ b/test/CodeGen/CellSPU/icmp32.ll @@ -322,10 +322,8 @@ entry: define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { ; CHECK: icmp_ult_immed04_i32: -; CHECK: ila -; CHECK: ceq -; CHECK: clgt -; CHECK: nor +; CHECK: rotmi +; CHECK: ceqi ; CHECK: selb $3, $5, $4, $3 entry: diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll index 8343cece45..eb06327f55 100644 --- a/test/CodeGen/X86/cmp.ll +++ b/test/CodeGen/X86/cmp.ll @@ -96,7 +96,7 @@ entry: ; CHECK: test7: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi -; CHECK: testl %edi, %edi +; CHECK: testq %rdi, %rdi ; CHECK: sete %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 @@ -108,7 +108,7 @@ entry: ; CHECK: test8: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi -; CHECK: cmpl $3, %edi +; CHECK: cmpq $3, %rdi %lnot = icmp ult i64 %res, 12884901888 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext @@ -119,7 +119,7 @@ entry: ; CHECK: test9: ; CHECK-NOT: movabsq ; CHECK: shrq $33, %rdi -; CHECK: testl %edi, %edi +; CHECK: testq %rdi, %rdi ; CHECK: sete %lnot = icmp ult i64 %res, 8589934592 %lnot.ext = zext i1 %lnot to i32 @@ -131,8 +131,8 @@ entry: ; CHECK: test10: ; CHECK-NOT: movabsq ; CHECK: shrq $32, %rdi -; CHECK: cmpl $1, %edi -; CHECK: setae +; CHECK: testq %rdi, %rdi +; CHECK: setne %lnot = icmp uge i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext |