diff options
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 17 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/2013-05-17-CallFrame.ll | 22 |
2 files changed, 27 insertions, 12 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 219d906c38..707fe7b4a6 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1411,6 +1411,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::BSWAP, MVT::i64, Expand); setOperationAction(ISD::ROTL , MVT::i64, Expand); setOperationAction(ISD::ROTR , MVT::i64, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); } // FIXME: There are instructions available for ATOMIC_FENCE @@ -2289,20 +2290,23 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); } -static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { +static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, + bool is64Bit) { SDValue Chain = Op.getOperand(0); // Legalize the chain. SDValue Size = Op.getOperand(1); // Legalize the size. + EVT VT = Size->getValueType(0); SDLoc dl(Op); unsigned SPReg = SP::O6; - SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); - SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); + SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain // The resultant pointer is actually 16 words from the bottom of the stack, // to provide a register spill area. - SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, - DAG.getConstant(96, MVT::i32)); + unsigned regSpillArea = (is64Bit) ? 128 : 96; + SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, + DAG.getConstant(regSpillArea, VT)); SDValue Ops[2] = { NewVal, Chain }; return DAG.getMergeValues(Ops, 2, dl); } @@ -2626,7 +2630,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const { hasHardQuad); case ISD::VASTART: return LowerVASTART(Op, DAG, *this); case ISD::VAARG: return LowerVAARG(Op, DAG); - case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, + is64Bit); case ISD::LOAD: return LowerF128Load(Op, DAG); case ISD::STORE: return LowerF128Store(Op, DAG); diff --git a/test/CodeGen/SPARC/2013-05-17-CallFrame.ll b/test/CodeGen/SPARC/2013-05-17-CallFrame.ll index 9e9e8216a8..9c74aa0c7c 100644 --- a/test/CodeGen/SPARC/2013-05-17-CallFrame.ll +++ b/test/CodeGen/SPARC/2013-05-17-CallFrame.ll @@ -1,10 +1,20 @@ -; RUN: llc -march=sparc < %s | FileCheck %s +; RUN: llc -march=sparc < %s | FileCheck %s --check-prefix=V8 +; RUN: llc -march=sparcv9 < %s | FileCheck %s --check-prefix=SPARC64 + +; V8-LABEL: variable_alloca_with_adj_call_stack +; V8: save %sp, -96, %sp +; V8: add {{.+}}, 96, %o0 +; V8: add %sp, -16, %sp +; V8: call foo +; V8: add %sp, 16, %sp + +; SPARC64-LABEL: variable_alloca_with_adj_call_stack +; SPARC64: save %sp, -128, %sp +; SPARC64: add {{.+}}, 128, %o0 +; SPARC64: add %sp, -80, %sp +; SPARC64: call foo +; SPARC64: add %sp, 80, %sp -; CHECK: variable_alloca_with_adj_call_stack -; CHECK: save %sp, -96, %sp -; CHECK: add %sp, -16, %sp -; CHECK: call foo -; CHECK: add %sp, 16, %sp define void @variable_alloca_with_adj_call_stack(i32 %num) { entry: %0 = alloca i8, i32 %num, align 8 |