diff options
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/rem.ll | 16 |
2 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 707fe7b4a6..1b56757c1d 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1462,6 +1462,13 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + if (Subtarget->is64Bit()) { + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::MULHU, MVT::i64, Expand); + setOperationAction(ISD::MULHS, MVT::i64, Expand); + } + // VASTART needs to be custom lowered to use the VarArgsFrameIndex. setOperationAction(ISD::VASTART , MVT::Other, Custom); // VAARG needs to be lowered to not do unaligned accesses for doubles. diff --git a/test/CodeGen/SPARC/rem.ll b/test/CodeGen/SPARC/rem.ll index 71f62e4fc1..abef1fc112 100644 --- a/test/CodeGen/SPARC/rem.ll +++ b/test/CodeGen/SPARC/rem.ll @@ -21,3 +21,19 @@ define i64 @test2(i64 %X, i64 %Y) { %tmp1 = urem i64 %X, %Y ret i64 %tmp1 } + +; PR18150 +; CHECK-LABEL: test3 +; CHECK: sethi 2545, [[R0:%[gilo][0-7]]] +; CHECK: or [[R0]], 379, [[R1:%[gilo][0-7]]] +; CHECK: mulx %o0, [[R1]], [[R2:%[gilo][0-7]]] +; CHECK: udivx [[R2]], 1021, [[R3:%[gilo][0-7]]] +; CHECK: mulx [[R3]], 1021, [[R4:%[gilo][0-7]]] +; CHECK: sub [[R2]], [[R4]], %o0 + +define i64 @test3(i64 %b) { +entry: + %mul = mul i64 %b, 2606459 + %rem = urem i64 %mul, 1021 + ret i64 %rem +} |