diff options
26 files changed, 200 insertions, 192 deletions
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 308026dd86..30abcd7b92 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -35,18 +35,17 @@ namespace llvm { /// /// This is an ImmutablePass solely for the purpose of exposing CodeGen options /// to the internals of other CodeGen passes. -/// -/// FIXME: Why are we passing the DisableVerify flags around instead of setting -/// an options in the target machine, like all the other driver options? class TargetPassConfig : public ImmutablePass { protected: TargetMachine *TM; PassManagerBase &PM; + + // Target Pass Options + // bool DisableVerify; public: - TargetPassConfig(TargetMachine *tm, PassManagerBase &pm, - bool DisableVerifyFlag); + TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); // Dummy constructor. TargetPassConfig(); @@ -59,17 +58,37 @@ public: return *static_cast<TMC*>(TM); } + const TargetLowering *getTargetLowering() const { + return TM->getTargetLowering(); + } + CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } - const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); } + void setDisableVerify(bool disable) { DisableVerify = disable; } + + /// Add common target configurable passes that perform LLVM IR to IR + /// transforms following machine independent optimization. + virtual void addIRPasses(); + + /// Add common passes that perform LLVM IR to IR transforms in preparation for + /// instruction selection. + virtual void addISelPrepare(); + + /// addInstSelector - This method should install an instruction selector pass, + /// which converts from LLVM code to machine instructions. + virtual bool addInstSelector() { + return true; + } /// Add the complete, standard set of LLVM CodeGen passes. /// Fully developed targets will not generally override this. - virtual bool addCodeGenPasses(MCContext *&OutContext); - + virtual void addMachinePasses(); protected: - /// Convenient points in the common codegen pass pipeline for inserting - /// passes, and major CodeGen stages that some targets may override. + /// Methods with trivial inline returns are convenient points in the common + /// codegen pass pipeline where targets may insert passes. Methods with + /// out-of-line standard implementations are major CodeGen stages called by + /// addMachinePasses. Some targets may override major stages when inserting + /// passes is insufficient, but maintaining overriden stages is more work. /// /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM @@ -78,12 +97,6 @@ protected: return true; } - /// addInstSelector - This method should install an instruction selector pass, - /// which converts from LLVM code to machine instructions. - virtual bool addInstSelector() { - return true; - } - /// addPreRegAlloc - This method may be implemented by targets that want to /// run passes immediately before register allocation. This should return /// true if -print-machineinstrs should print after these passes. diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index afb15c0895..d4535dbe9e 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -286,8 +286,7 @@ protected: // Can only create subclasses. public: /// createPassConfig - Create a pass configuration object to be used by /// addPassToEmitX methods for generating a pipeline of CodeGen passes. - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index b10dab4de8..de69526a1e 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -11,18 +11,24 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Target/TargetMachine.h" +#include "llvm/Transforms/Scalar.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunctionAnalysis.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetLoweringObjectFile.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" @@ -30,6 +36,13 @@ #include "llvm/Support/TargetRegistry.h" using namespace llvm; +// Enable or disable FastISel. Both options are needed, because +// FastISel is enabled by default with -fast, and we wish to be +// able to enable or disable fast-isel independently from -O0. +static cl::opt<cl::boolOrDefault> +EnableFastISelOption("fast-isel", cl::Hidden, + cl::desc("Enable the \"fast\" instruction selector")); + static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden, cl::desc("Show encoding in .s output")); static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden, @@ -65,17 +78,84 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, "and that InitializeAllTargetMCs() is being invoked!"); } +/// Turn exception handling constructs into something the code generators can +/// handle. +static void addPassesToHandleExceptions(TargetMachine *TM, + PassManagerBase &PM) { + switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { + case ExceptionHandling::SjLj: + // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both + // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, + // catch info can get misplaced when a selector ends up more than one block + // removed from the parent invoke(s). This could happen when a landing + // pad is shared by multiple invokes and is also a target of a normal + // edge from elsewhere. + PM.add(createSjLjEHPass(TM->getTargetLowering())); + // FALLTHROUGH + case ExceptionHandling::DwarfCFI: + case ExceptionHandling::ARM: + case ExceptionHandling::Win64: + PM.add(createDwarfEHPass(TM)); + break; + case ExceptionHandling::None: + PM.add(createLowerInvokePass(TM->getTargetLowering())); + + // The lower invoke pass may create unreachable code. Remove it. + PM.add(createUnreachableBlockEliminationPass()); + break; + } +} + +/// addPassesToX helper drives creation and initialization of TargetPassConfig. +static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM, + PassManagerBase &PM, + bool DisableVerify) { + // Targets may override createPassConfig to provide a target-specific sublass. + TargetPassConfig *PassConfig = TM->createPassConfig(PM); + + // Set PassConfig options provided by TargetMachine. + PassConfig->setDisableVerify(DisableVerify); + + PassConfig->addIRPasses(); + + addPassesToHandleExceptions(TM, PM); + + PassConfig->addISelPrepare(); + + // Install a MachineModuleInfo class, which is an immutable pass that holds + // all the per-module stuff we're generating, including MCContext. + MachineModuleInfo *MMI = + new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(), + &TM->getTargetLowering()->getObjFileLowering()); + PM.add(MMI); + MCContext *Context = &MMI->getContext(); // Return the MCContext specifically by-ref. + + // Set up a MachineFunction for the rest of CodeGen to work on. + PM.add(new MachineFunctionAnalysis(*TM)); + + // Enable FastISel with -fast, but allow that to be overridden. + if (EnableFastISelOption == cl::BOU_TRUE || + (TM->getOptLevel() == CodeGenOpt::None && + EnableFastISelOption != cl::BOU_FALSE)) + TM->setFastISel(true); + + // Ask the target for an isel. + if (PassConfig->addInstSelector()) + return NULL; + + PassConfig->addMachinePasses(); + + return Context; +} + bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, CodeGenFileType FileType, bool DisableVerify) { // Add common CodeGen passes. - MCContext *Context = 0; - TargetPassConfig *PassConfig = createPassConfig(PM, DisableVerify); - PM.add(PassConfig); - if (PassConfig->addCodeGenPasses(Context)) + MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify); + if (!Context) return true; - assert(Context != 0 && "Failed to get MCContext"); if (hasMCSaveTempLabels()) Context->setAllowTemporaryLabels(false); @@ -156,9 +236,8 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, JITCodeEmitter &JCE, bool DisableVerify) { // Add common CodeGen passes. - MCContext *Ctx = 0; - OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify)); - if (PassConfig->addCodeGenPasses(Ctx)) + MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify); + if (!Context) return true; addCodeEmitter(PM, JCE); @@ -177,8 +256,8 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, raw_ostream &Out, bool DisableVerify) { // Add common CodeGen passes. - OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify)); - if (PassConfig->addCodeGenPasses(Ctx)) + Ctx = addPassesToGenerateCode(this, PM, DisableVerify); + if (!Ctx) return true; if (hasMCSaveTempLabels()) diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index 739ff60d3a..21d87143fe 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -17,16 +17,11 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/GCStrategy.h" -#include "llvm/CodeGen/MachineFunctionAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/MC/MCAsmInfo.h" #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -77,13 +72,6 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); -// Enable or disable FastISel. Both options are needed, because -// FastISel is enabled by default with -fast, and we wish to be -// able to enable or disable fast-isel independently from -O0. -static cl::opt<cl::boolOrDefault> -EnableFastISelOption("fast-isel", cl::Hidden, - cl::desc("Enable the \"fast\" instruction selector")); - //===---------------------------------------------------------------------===// /// TargetPassConfig //===---------------------------------------------------------------------===// @@ -95,9 +83,8 @@ char TargetPassConfig::ID = 0; // Out of line virtual method. TargetPassConfig::~TargetPassConfig() {} -TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm, - bool DisableVerifyFlag) - : ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(DisableVerifyFlag) { +TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) + : ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(false) { // Register all target independent codegen passes to activate their PassIDs, // including this pass itself. initializeCodeGen(*PassRegistry::getPassRegistry()); @@ -107,9 +94,8 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm, /// addPassToEmitX methods for generating a pipeline of CodeGen passes. /// /// Targets may override this to extend TargetPassConfig. -TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new TargetPassConfig(this, PM, DisableVerify); +TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { + return new TargetPassConfig(this, PM); } TargetPassConfig::TargetPassConfig() @@ -117,6 +103,9 @@ TargetPassConfig::TargetPassConfig() llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); } +void TargetPassConfig::addCommonPass(char &ID) { + // FIXME: about to be implemented. +} void TargetPassConfig::printNoVerify(const char *Banner) const { if (TM->shouldPrintMachineCode()) @@ -131,12 +120,9 @@ void TargetPassConfig::printAndVerify(const char *Banner) const { PM.add(createMachineVerifierPass(Banner)); } -/// addCodeGenPasses - Add standard LLVM codegen passes used for both -/// emitting to assembly files or machine code output. -/// -bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) { - // Standard LLVM-Level Passes. - +/// Add common target configurable passes that perform LLVM IR to IR transforms +/// following machine independent optimization. +void TargetPassConfig::addIRPasses() { // Basic AliasAnalysis support. // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that // BasicAliasAnalysis wins if they disagree. This is intended to help @@ -160,32 +146,11 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) { // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); +} - // Turn exception handling constructs into something the code generators can - // handle. - switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { - case ExceptionHandling::SjLj: - // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both - // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, - // catch info can get misplaced when a selector ends up more than one block - // removed from the parent invoke(s). This could happen when a landing - // pad is shared by multiple invokes and is also a target of a normal - // edge from elsewhere. - PM.add(createSjLjEHPass(getTargetLowering())); - // FALLTHROUGH - case ExceptionHandling::DwarfCFI: - case ExceptionHandling::ARM: - case ExceptionHandling::Win64: - PM.add(createDwarfEHPass(TM)); - break; - case ExceptionHandling::None: - PM.add(createLowerInvokePass(getTargetLowering())); - - // The lower invoke pass may create unreachable code. Remove it. - PM.add(createUnreachableBlockEliminationPass()); - break; - } - +/// Add common passes that perform LLVM IR to IR transforms in preparation for +/// instruction selection. +void TargetPassConfig::addISelPrepare() { if (getOptLevel() != CodeGenOpt::None && !DisableCGP) PM.add(createCodeGenPreparePass(getTargetLowering())); @@ -202,30 +167,9 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) { // to ensure that the IR is valid. if (!DisableVerify) PM.add(createVerifierPass()); +} - // Standard Lower-Level Passes. - - // Install a MachineModuleInfo class, which is an immutable pass that holds - // all the per-module stuff we're generating, including MCContext. - MachineModuleInfo *MMI = - new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(), - &getTargetLowering()->getObjFileLowering()); - PM.add(MMI); - OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. - - // Set up a MachineFunction for the rest of CodeGen to work on. - PM.add(new MachineFunctionAnalysis(*TM)); - - // Enable FastISel with -fast, but allow that to be overridden. - if (EnableFastISelOption == cl::BOU_TRUE || - (getOptLevel() == CodeGenOpt::None && - EnableFastISelOption != cl::BOU_FALSE)) - TM->setFastISel(true); - - // Ask the target for an isel. - if (addInstSelector()) - return true; - +void TargetPassConfig::addMachinePasses() { // Print the instruction selected machine code... printAndVerify("After Instruction Selection"); @@ -356,8 +300,6 @@ bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) { if (addPreEmitPass()) printNoVerify("After PreEmit passes"); - - return false; } //===---------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index cfe45584ed..35d18d3a5b 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -111,9 +111,8 @@ namespace { /// ARM Code Generator Pass Configuration Options. class ARMPassConfig : public TargetPassConfig { public: - ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} ARMBaseTargetMachine &getARMTargetMachine() const { return getTM<ARMBaseTargetMachine>(); @@ -131,9 +130,8 @@ public: }; } // namespace -TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new ARMPassConfig(this, PM, DisableVerify); +TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) { + return new ARMPassConfig(this, PM); } bool ARMPassConfig::addPreISel() { diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 5e70b7186d..abcdb24c0c 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -52,7 +52,7 @@ public: } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE); }; diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 83e22f624c..a12ba10c33 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -55,9 +55,8 @@ namespace { /// SPU Code Generator Pass Configuration Options. class SPUPassConfig : public TargetPassConfig { public: - SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} SPUTargetMachine &getSPUTargetMachine() const { return getTM<SPUTargetMachine>(); @@ -68,9 +67,8 @@ public: }; } // namespace -TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new SPUPassConfig(this, PM, DisableVerify); +TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SPUPassConfig(this, PM); } bool SPUPassConfig::addInstSelector() { diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index 7eeb128aca..5daf7a5cfe 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -82,8 +82,7 @@ public: } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; } // end namespace llvm diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 83f0b40af6..360446ad59 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -80,9 +80,8 @@ namespace { /// Hexagon Code Generator Pass Configuration Options. class HexagonPassConfig : public TargetPassConfig { public: - HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} HexagonTargetMachine &getHexagonTargetMachine() const { return getTM<HexagonTargetMachine>(); @@ -96,9 +95,8 @@ public: }; } // namespace -TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new HexagonPassConfig(this, PM, DisableVerify); +TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { + return new HexagonPassConfig(this, PM); } bool HexagonPassConfig::addInstSelector() { diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index d1c76db30b..70bea56cfd 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -72,8 +72,7 @@ public: // Pass Pipeline Configuration. virtual bool addPassesForOptimizations(PassManagerBase &PM); - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; extern bool flag_aligned_memcpy; diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/lib/Target/MBlaze/MBlazeTargetMachine.cpp index aad3500ffd..5c074243dd 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.cpp +++ b/lib/Target/MBlaze/MBlazeTargetMachine.cpp @@ -49,9 +49,8 @@ namespace { /// MBlaze Code Generator Pass Configuration Options. class MBlazePassConfig : public TargetPassConfig { public: - MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} MBlazeTargetMachine &getMBlazeTargetMachine() const { return getTM<MBlazeTargetMachine>(); @@ -62,9 +61,8 @@ public: }; } // namespace -TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new MBlazePassConfig(this, PM, DisableVerify); +TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) { + return new MBlazePassConfig(this, PM); } // Install an instruction selector pass using diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.h b/lib/Target/MBlaze/MBlazeTargetMachine.h index 58fcbfd671..512bcd0a31 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.h +++ b/lib/Target/MBlaze/MBlazeTargetMachine.h @@ -79,8 +79,7 @@ namespace llvm { } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; } // End llvm namespace diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp index a2e97f11e5..af62e4813a 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -42,9 +42,8 @@ namespace { /// MSP430 Code Generator Pass Configuration Options. class MSP430PassConfig : public TargetPassConfig { public: - MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} MSP430TargetMachine &getMSP430TargetMachine() const { return getTM<MSP430TargetMachine>(); @@ -55,9 +54,8 @@ public: }; } // namespace -TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new MSP430PassConfig(this, PM, DisableVerify); +TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) { + return new MSP430PassConfig(this, PM); } bool MSP430PassConfig::addInstSelector() { diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index 19b7bf1b71..ed09424d7c 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -62,8 +62,7 @@ public: return &TSInfo; } - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; // MSP430TargetMachine. } // end namespace llvm diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index e48c3745f6..ff766faad6 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -93,9 +93,8 @@ namespace { /// Mips Code Generator Pass Configuration Options. class MipsPassConfig : public TargetPassConfig { public: - MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} MipsTargetMachine &getMipsTargetMachine() const { return getTM<MipsTargetMachine>(); @@ -112,9 +111,8 @@ public: }; } // namespace -TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new MipsPassConfig(this, PM, DisableVerify); +TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { + return new MipsPassConfig(this, PM); } // Install an instruction selector pass using diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index b2a609c5c5..fab576d7da 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -68,8 +68,7 @@ namespace llvm { } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp index cf45c8fe47..5a14e8accd 100644 --- a/lib/Target/PTX/PTXTargetMachine.cpp +++ b/lib/Target/PTX/PTXTargetMachine.cpp @@ -109,8 +109,8 @@ namespace { /// PTX Code Generator Pass Configuration Options. class PTXPassConfig : public TargetPassConfig { public: - PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM, bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} PTXTargetMachine &getPTXTargetMachine() const { return getTM<PTXTargetMachine>(); @@ -122,9 +122,8 @@ public: }; } // namespace -TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new PTXPassConfig(this, PM, DisableVerify); +TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) { + return new PTXPassConfig(this, PM); } bool PTXPassConfig::addInstSelector() { @@ -146,7 +145,13 @@ bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM, // Add common CodeGen passes. MCContext *Context = 0; - OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify)); + + // FIXME: soon this will be converted to use the exposed TargetPassConfig API. + OwningPtr<PTXPassConfig> PassConfig( + static_cast<PTXPassConfig*>(createPassConfig(PM))); + + PassConfig->setDisableVerify(DisableVerify); + if (PassConfig->addCodeGenPasses(Context)) return true; assert(Context != 0 && "Failed to get MCContext"); diff --git a/lib/Target/PTX/PTXTargetMachine.h b/lib/Target/PTX/PTXTargetMachine.h index 3e991399ab..e1b7b0c0ba 100644 --- a/lib/Target/PTX/PTXTargetMachine.h +++ b/lib/Target/PTX/PTXTargetMachine.h @@ -81,8 +81,7 @@ class PTXTargetMachine : public LLVMTargetMachine { } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; // class PTXTargetMachine diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 9298661377..f5be148399 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -70,9 +70,8 @@ namespace { /// PPC Code Generator Pass Configuration Options. class PPCPassConfig : public TargetPassConfig { public: - PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} PPCTargetMachine &getPPCTargetMachine() const { return getTM<PPCTargetMachine>(); @@ -84,9 +83,8 @@ public: }; } // namespace -TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new PPCPassConfig(this, PM, DisableVerify); +TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { + return new PPCPassConfig(this, PM); } bool PPCPassConfig::addInstSelector() { diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 2877201ed7..4a2fa41958 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -67,8 +67,7 @@ public: } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); }; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index f45de4b145..80a3be6785 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -42,9 +42,8 @@ namespace { /// Sparc Code Generator Pass Configuration Options. class SparcPassConfig : public TargetPassConfig { public: - SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} SparcTargetMachine &getSparcTargetMachine() const { return getTM<SparcTargetMachine>(); @@ -55,9 +54,8 @@ public: }; } // namespace -TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new SparcPassConfig(this, PM, DisableVerify); +TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SparcPassConfig(this, PM); } bool SparcPassConfig::addInstSelector() { diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 2622af25e5..b203dfa489 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -55,8 +55,7 @@ public: virtual const TargetData *getTargetData() const { return &DataLayout; } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; /// SparcV8TargetMachine - Sparc 32-bit target machine diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 0881735137..f4b7a6277a 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -121,9 +121,8 @@ namespace { /// X86 Code Generator Pass Configuration Options. class X86PassConfig : public TargetPassConfig { public: - X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} X86TargetMachine &getX86TargetMachine() const { return getTM<X86TargetMachine>(); @@ -140,9 +139,8 @@ public: }; } // namespace -TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new X86PassConfig(this, PM, DisableVerify); +TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { + return new X86PassConfig(this, PM); } bool X86PassConfig::addInstSelector() { diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 9450706f75..143caba5bd 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -71,8 +71,7 @@ public: } // Set up the pass pipeline. - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index a42acf1880..f65297e54a 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -39,9 +39,8 @@ namespace { /// XCore Code Generator Pass Configuration Options. class XCorePassConfig : public TargetPassConfig { public: - XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM, - bool DisableVerifyFlag) - : TargetPassConfig(TM, PM, DisableVerifyFlag) {} + XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} XCoreTargetMachine &getXCoreTargetMachine() const { return getTM<XCoreTargetMachine>(); @@ -51,9 +50,8 @@ public: }; } // namespace -TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM, - bool DisableVerify) { - return new XCorePassConfig(this, PM, DisableVerify); +TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) { + return new XCorePassConfig(this, PM); } bool XCorePassConfig::addInstSelector() { diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index aafd86e90a..2c174f49d2 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -56,8 +56,7 @@ public: virtual const TargetData *getTargetData() const { return &DataLayout; } // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, - bool DisableVerify); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; } // end namespace llvm |