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-rw-r--r--include/llvm/IR/IntrinsicsAArch64.td8
-rw-r--r--lib/Target/AArch64/AArch64InstrFormats.td44
-rw-r--r--lib/Target/AArch64/AArch64InstrNEON.td122
-rw-r--r--lib/Target/AArch64/AArch64RegisterInfo.td4
-rw-r--r--test/CodeGen/AArch64/neon-crypto.ll147
-rw-r--r--test/MC/AArch64/neon-crypto.s42
-rw-r--r--test/MC/AArch64/neon-diagnostics.s106
7 files changed, 468 insertions, 5 deletions
diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td
index 8083b867d1..b66bdcc01c 100644
--- a/include/llvm/IR/IntrinsicsAArch64.td
+++ b/include/llvm/IR/IntrinsicsAArch64.td
@@ -271,4 +271,12 @@ def int_aarch64_neon_vcvtf32_n_u32 :
Intrinsic<[llvm_v1f32_ty], [llvm_v1i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_aarch64_neon_vcvtf64_n_u64 :
Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
+class Neon_SHA_Intrinsic
+ : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+
+def int_aarch64_neon_sha1c : Neon_SHA_Intrinsic;
+def int_aarch64_neon_sha1m : Neon_SHA_Intrinsic;
+def int_aarch64_neon_sha1p : Neon_SHA_Intrinsic;
}
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index 4782b55de0..b3e114a01b 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1279,5 +1279,49 @@ class NeonI_ScalarShiftImm<bit u, bits<5> opcode,
// Inherit Rd in 4-0
}
+// Format AdvSIMD crypto AES
+class NeonI_Crypto_AES<bits<2> size, bits<5> opcode,
+ dag outs, dag ins, string asmstr,
+ list<dag> patterns, InstrItinClass itin>
+ : A64InstRdn<outs, ins, asmstr, patterns, itin> {
+ let Inst{31-24} = 0b01001110;
+ let Inst{23-22} = size;
+ let Inst{21-17} = 0b10100;
+ let Inst{16-12} = opcode;
+ let Inst{11-10} = 0b10;
+ // Inherit Rn in 9-5
+ // Inherit Rd in 4-0
+}
+
+// Format AdvSIMD crypto SHA
+class NeonI_Crypto_SHA<bits<2> size, bits<5> opcode,
+ dag outs, dag ins, string asmstr,
+ list<dag> patterns, InstrItinClass itin>
+ : A64InstRdn<outs, ins, asmstr, patterns, itin> {
+ let Inst{31-24} = 0b01011110;
+ let Inst{23-22} = size;
+ let Inst{21-17} = 0b10100;
+ let Inst{16-12} = opcode;
+ let Inst{11-10} = 0b10;
+ // Inherit Rn in 9-5
+ // Inherit Rd in 4-0
+}
+
+// Format AdvSIMD crypto 3V SHA
+class NeonI_Crypto_3VSHA<bits<2> size, bits<3> opcode,
+ dag outs, dag ins, string asmstr,
+ list<dag> patterns, InstrItinClass itin>
+ : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
+ let Inst{31-24} = 0b01011110;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b0;
+ // Inherit Rm in 20-16
+ let Inst{15} = 0b0;
+ let Inst{14-12} = opcode;
+ let Inst{11-10} = 0b00;
+ // Inherit Rn in 9-5
+ // Inherit Rd in 4-0
+}
+
}
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index dbae303d56..4cb5da6b8a 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -2663,11 +2663,14 @@ defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
multiclass NeonI_Op_High<SDPatternOperator op> {
def _16B : PatFrag<(ops node:$Rn, node:$Rm),
- (op (v8i8 (Neon_High16B node:$Rn)), (v8i8 (Neon_High16B node:$Rm)))>;
+ (op (v8i8 (Neon_High16B node:$Rn)),
+ (v8i8 (Neon_High16B node:$Rm)))>;
def _8H : PatFrag<(ops node:$Rn, node:$Rm),
- (op (v4i16 (Neon_High8H node:$Rn)), (v4i16 (Neon_High8H node:$Rm)))>;
+ (op (v4i16 (Neon_High8H node:$Rn)),
+ (v4i16 (Neon_High8H node:$Rm)))>;
def _4S : PatFrag<(ops node:$Rn, node:$Rm),
- (op (v2i32 (Neon_High4S node:$Rn)), (v2i32 (Neon_High4S node:$Rm)))>;
+ (op (v2i32 (Neon_High4S node:$Rn)),
+ (v2i32 (Neon_High4S node:$Rm)))>;
}
defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
@@ -5793,3 +5796,116 @@ def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
(v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
(v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
+
+// Crypto Class
+class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
+ string asmop, SDPatternOperator opnode>
+ : NeonI_Crypto_AES<size, opcode,
+ (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
+ asmop # "\t$Rd.16b, $Rn.16b",
+ [(set (v16i8 VPR128:$Rd),
+ (v16i8 (opnode (v16i8 VPR128:$src),
+ (v16i8 VPR128:$Rn))))],
+ NoItinerary>{
+ let Constraints = "$src = $Rd";
+}
+
+def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
+def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
+
+class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
+ string asmop, SDPatternOperator opnode>
+ : NeonI_Crypto_AES<size, opcode,
+ (outs VPR128:$Rd), (ins VPR128:$Rn),
+ asmop # "\t$Rd.16b, $Rn.16b",
+ [(set (v16i8 VPR128:$Rd),
+ (v16i8 (opnode (v16i8 VPR128:$Rn))))],
+ NoItinerary>;
+
+def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
+def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
+
+class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
+ string asmop, SDPatternOperator opnode>
+ : NeonI_Crypto_SHA<size, opcode,
+ (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
+ asmop # "\t$Rd.4s, $Rn.4s",
+ [(set (v4i32 VPR128:$Rd),
+ (v4i32 (opnode (v4i32 VPR128:$src),
+ (v4i32 VPR128:$Rn))))],
+ NoItinerary> {
+ let Constraints = "$src = $Rd";
+}
+
+def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
+ int_arm_neon_sha1su1>;
+def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
+ int_arm_neon_sha256su0>;
+
+class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
+ string asmop, SDPatternOperator opnode>
+ : NeonI_Crypto_SHA<size, opcode,
+ (outs FPR32:$Rd), (ins FPR32:$Rn),
+ asmop # "\t$Rd, $Rn",
+ [(set (v1i32 FPR32:$Rd),
+ (v1i32 (opnode (v1i32 FPR32:$Rn))))],
+ NoItinerary>;
+
+def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
+
+class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
+ SDPatternOperator opnode>
+ : NeonI_Crypto_3VSHA<size, opcode,
+ (outs VPR128:$Rd),
+ (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
+ asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
+ [(set (v4i32 VPR128:$Rd),
+ (v4i32 (opnode (v4i32 VPR128:$src),
+ (v4i32 VPR128:$Rn),
+ (v4i32 VPR128:$Rm))))],
+ NoItinerary> {
+ let Constraints = "$src = $Rd";
+}
+
+def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
+ int_arm_neon_sha1su0>;
+def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
+ int_arm_neon_sha256su1>;
+
+class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
+ SDPatternOperator opnode>
+ : NeonI_Crypto_3VSHA<size, opcode,
+ (outs FPR128:$Rd),
+ (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
+ asmop # "\t$Rd, $Rn, $Rm.4s",
+ [(set (v4i32 FPR128:$Rd),
+ (v4i32 (opnode (v4i32 FPR128:$src),
+ (v4i32 FPR128:$Rn),
+ (v4i32 VPR128:$Rm))))],
+ NoItinerary> {
+ let Constraints = "$src = $Rd";
+}
+
+def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
+ int_arm_neon_sha256h>;
+def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
+ int_arm_neon_sha256h2>;
+
+class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
+ SDPatternOperator opnode>
+ : NeonI_Crypto_3VSHA<size, opcode,
+ (outs FPR128:$Rd),
+ (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
+ asmop # "\t$Rd, $Rn, $Rm.4s",
+ [(set (v4i32 FPR128:$Rd),
+ (v4i32 (opnode (v4i32 FPR128:$src),
+ (v1i32 FPR32:$Rn),
+ (v4i32 VPR128:$Rm))))],
+ NoItinerary> {
+ let Constraints = "$src = $Rd";
+}
+
+def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
+def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
+def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
+
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td
index 5e2b196397..7a7f943b37 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -164,7 +164,7 @@ def FPR64 : RegisterClass<"AArch64",
64, (sequence "D%u", 0, 31)>;
def FPR128 : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 31)>;
def FPR64Lo : RegisterClass<"AArch64",
@@ -172,7 +172,7 @@ def FPR64Lo : RegisterClass<"AArch64",
64, (sequence "D%u", 0, 15)>;
def FPR128Lo : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 15)>;
//===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/AArch64/neon-crypto.ll b/test/CodeGen/AArch64/neon-crypto.ll
new file mode 100644
index 0000000000..e4ae22786d
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-crypto.ll
@@ -0,0 +1,147 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32>, <1 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32>, <1 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32>, <1 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>) #1
+
+declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>) #1
+
+declare <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32>) #1
+
+declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>) #1
+
+declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>) #1
+
+declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>) #1
+
+declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1
+
+define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
+; CHECK: test_vaeseq_u8:
+; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+entry:
+ %aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key)
+ ret <16 x i8> %aese.i
+}
+
+define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) {
+; CHECK: test_vaesdq_u8:
+; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+entry:
+ %aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %data, <16 x i8> %key)
+ ret <16 x i8> %aesd.i
+}
+
+define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) {
+; CHECK: test_vaesmcq_u8:
+; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+entry:
+ %aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %data)
+ ret <16 x i8> %aesmc.i
+}
+
+define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) {
+; CHECK: test_vaesimcq_u8:
+; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+entry:
+ %aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %data)
+ ret <16 x i8> %aesimc.i
+}
+
+define i32 @test_vsha1h_u32(i32 %hash_e) {
+; CHECK: test_vsha1h_u32:
+; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
+entry:
+ %sha1h.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
+ %sha1h1.i = tail call <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32> %sha1h.i)
+ %0 = extractelement <1 x i32> %sha1h1.i, i32 0
+ ret i32 %0
+}
+
+define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) {
+; CHECK: test_vsha1su1q_u32:
+; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+entry:
+ %sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w12_15)
+ ret <4 x i32> %sha1su12.i
+}
+
+define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) {
+; CHECK: test_vsha256su0q_u32:
+; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+entry:
+ %sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7)
+ ret <4 x i32> %sha256su02.i
+}
+
+define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
+; CHECK: test_vsha1cq_u32:
+; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
+entry:
+ %sha1c.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
+ %sha1c1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32> %hash_abcd, <1 x i32> %sha1c.i, <4 x i32> %wk)
+ ret <4 x i32> %sha1c1.i
+}
+
+define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
+; CHECK: test_vsha1pq_u32:
+; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
+entry:
+ %sha1p.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
+ %sha1p1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32> %hash_abcd, <1 x i32> %sha1p.i, <4 x i32> %wk)
+ ret <4 x i32> %sha1p1.i
+}
+
+define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
+; CHECK: test_vsha1mq_u32:
+; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
+entry:
+ %sha1m.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
+ %sha1m1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32> %hash_abcd, <1 x i32> %sha1m.i, <4 x i32> %wk)
+ ret <4 x i32> %sha1m1.i
+}
+
+define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) {
+; CHECK: test_vsha1su0q_u32:
+; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+entry:
+ %sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
+ ret <4 x i32> %sha1su03.i
+}
+
+define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
+; CHECK: test_vsha256hq_u32:
+; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
+entry:
+ %sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
+ ret <4 x i32> %sha256h3.i
+}
+
+define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
+; CHECK: test_vsha256h2q_u32:
+; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
+entry:
+ %sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
+ ret <4 x i32> %sha256h23.i
+}
+
+define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
+; CHECK: test_vsha256su1q_u32:
+; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+entry:
+ %sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
+ ret <4 x i32> %sha256su13.i
+}
+
diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s
new file mode 100644
index 0000000000..df6eee851d
--- /dev/null
+++ b/test/MC/AArch64/neon-crypto.s
@@ -0,0 +1,42 @@
+// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//------------------------------------------------------------------------------
+// Instructions for crypto
+//------------------------------------------------------------------------------
+
+ aese v0.16b, v1.16b
+ aesd v0.16b, v1.16b
+ aesmc v0.16b, v1.16b
+ aesimc v0.16b, v1.16b
+
+// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]
+// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]
+// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]
+// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e]
+
+ sha1h s0, s1
+ sha1su1 v0.4s, v1.4s
+ sha256su0 v0.4s, v1.4s
+
+// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e]
+// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e]
+// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e]
+
+ sha1c q0, s1, v2.4s
+ sha1p q0, s1, v2.4s
+ sha1m q0, s1, v2.4s
+ sha1su0 v0.4s, v1.4s, v2.4s
+ sha256h q0, q1, v2.4s
+ sha256h2 q0, q1, v2.4s
+ sha256su1 v0.4s, v1.4s, v2.4s
+
+// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e]
+// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e]
+// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e]
+// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e]
+// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e]
+// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e]
+// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]
+
diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s
index a43287d94b..67a938ed77 100644
--- a/test/MC/AArch64/neon-diagnostics.s
+++ b/test/MC/AArch64/neon-diagnostics.s
@@ -5088,3 +5088,109 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ucvtf d21, s14, #64
// CHECK-ERROR: ^
+
+//----------------------------------------------------------------------
+// Scalar Unsigned Saturating Extract Narrow
+//----------------------------------------------------------------------
+
+ aese v0.8h, v1.8h
+ aese v0.4s, v1.4s
+ aese v0.2d, v1.2d
+ aesd v0.8h, v1.8h
+ aesmc v0.8h, v1.8h
+ aesimc v0.8h, v1.8h
+
+// CHECK: error: invalid operand for instruction
+// CHECK: aese v0.8h, v1.8h
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: aese v0.4s, v1.4s
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: aese v0.2d, v1.2d
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: aesd v0.8h, v1.8h
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: aesmc v0.8h, v1.8h
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: aesimc v0.8h, v1.8h
+// CHECK: ^
+
+ sha1h b0, b1
+ sha1h h0, h1
+ sha1h d0, d1
+ sha1h q0, q1
+ sha1su1 v0.16b, v1.16b
+ sha1su1 v0.8h, v1.8h
+ sha1su1 v0.2d, v1.2d
+ sha256su0 v0.16b, v1.16b
+
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1h b0, b1
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1h h0, h1
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1h d0, d1
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1h q0, q1
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su1 v0.16b, v1.16b
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su1 v0.8h, v1.8h
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su1 v0.2d, v1.2d
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha256su0 v0.16b, v1.16b
+// CHECK: ^
+
+ sha1c q0, q1, v2.4s
+ sha1p q0, q1, v2.4s
+ sha1m q0, q1, v2.4s
+ sha1su0 v0.16b, v1.16b, v2.16b
+ sha1su0 v0.8h, v1.8h, v2.8h
+ sha1su0 v0.2d, v1.2d, v2.2d
+ sha256h q0, q1, q2
+ sha256h v0.4s, v1.4s, v2.4s
+ sha256h2 q0, q1, q2
+ sha256su1 v0.16b, v1.16b, v2.16b
+
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1c q0, q1, v2.4s
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1p q0, q1, v2.4s
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1m q0, q1, v2.4s
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su0 v0.16b, v1.16b, v2.16b
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su0 v0.8h, v1.8h, v2.8h
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha1su0 v0.2d, v1.2d, v2.2d
+// CHECK: ^
+// CHECK: error: too few operands for instruction
+// CHECK: sha256h q0, q1, q2
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha256h v0.4s, v1.4s, v2.4s
+// CHECK: ^
+// CHECK: error: too few operands for instruction
+// CHECK: sha256h2 q0, q1, q2
+// CHECK: ^
+// CHECK: error: invalid operand for instruction
+// CHECK: sha256su1 v0.16b, v1.16b, v2.16b
+// CHECK: ^
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 15:11:37 +0000