diff options
46 files changed, 386 insertions, 157 deletions
diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h index a9e46371ad..3b53f205cd 100644 --- a/include/llvm/MC/MCSubtargetInfo.h +++ b/include/llvm/MC/MCSubtargetInfo.h @@ -16,6 +16,7 @@ #include "llvm/MC/SubtargetFeature.h" #include "llvm/MC/MCInstrItineraries.h" +#include <string> namespace llvm { @@ -26,6 +27,7 @@ class StringRef; /// MCSubtargetInfo - Generic base class for all target subtargets. /// class MCSubtargetInfo { + std::string TargetTriple; // Target triple const SubtargetFeatureKV *ProcFeatures; // Processor feature list const SubtargetFeatureKV *ProcDesc; // Processor descriptions const SubtargetInfoKV *ProcItins; // Scheduling itineraries @@ -34,18 +36,22 @@ class MCSubtargetInfo { const unsigned *ForwardingPathes; // Forwarding pathes unsigned NumFeatures; // Number of processor features unsigned NumProcs; // Number of processors - uint64_t FeatureBits; // Feature bits for current CPU + FS public: - void InitMCSubtargetInfo(StringRef CPU, StringRef FS, + void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *PI, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP); - /// getFeatureBits - Get the feature bits. + /// getTargetTriple - Return the target triple string. + StringRef getTargetTriple() const { + return TargetTriple; + } + + /// getFeatureBits - Return the feature bits. /// uint64_t getFeatureBits() const { return FeatureBits; diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h index 679b612fff..671000554c 100644 --- a/include/llvm/Target/TargetRegistry.h +++ b/include/llvm/Target/TargetRegistry.h @@ -89,8 +89,8 @@ namespace llvm { typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI); - typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const Target &T, - TargetMachine &TM, + typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const MCInstrInfo &II, + const MCSubtargetInfo &STI, MCContext &Ctx); typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T, const std::string &TT, @@ -352,10 +352,12 @@ namespace llvm { /// createCodeEmitter - Create a target specific code emitter. - MCCodeEmitter *createCodeEmitter(TargetMachine &TM, MCContext &Ctx) const { + MCCodeEmitter *createCodeEmitter(const MCInstrInfo &II, + const MCSubtargetInfo &STI, + MCContext &Ctx) const { if (!CodeEmitterCtorFn) return 0; - return CodeEmitterCtorFn(*this, TM, Ctx); + return CodeEmitterCtorFn(II, STI, Ctx); } /// createObjectStreamer - Create a target specific MCStreamer. @@ -971,9 +973,10 @@ namespace llvm { } private: - static MCCodeEmitter *Allocator(const Target &T, TargetMachine &TM, + static MCCodeEmitter *Allocator(const MCInstrInfo &II, + const MCSubtargetInfo &STI, MCContext &Ctx) { - return new CodeEmitterImpl(T, TM, Ctx); + return new CodeEmitterImpl(); } }; diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h index 7b969d0193..99c52ac746 100644 --- a/include/llvm/Target/TargetSelect.h +++ b/include/llvm/Target/TargetSelect.h @@ -27,6 +27,10 @@ extern "C" { #include "llvm/Config/Targets.def" #define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCInstrInfo(); +#include "llvm/Config/Targets.def" + +#define LLVM_TARGET(TargetName) \ void LLVMInitialize##TargetName##MCSubtargetInfo(); #include "llvm/Config/Targets.def" @@ -68,6 +72,17 @@ namespace llvm { #include "llvm/Config/Targets.def" } + /// InitializeAllMCInstrInfos - The main program should call this function + /// if it wants access to all available instruction infos for targets that + /// LLVM is configured to support, to make them available via the + /// TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCInstrInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCInstrInfo(); +#include "llvm/Config/Targets.def" + } + /// InitializeAllMCSubtargetInfos - The main program should call this function /// if it wants access to all available subtarget infos for targets that LLVM /// is configured to support, to make them available via the TargetRegistry. diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index e3337e4c12..63641a4579 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -24,10 +24,14 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetOptions.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Scalar.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" @@ -142,7 +146,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, MCCodeEmitter *MCE = 0; TargetAsmBackend *TAB = 0; if (ShowMCEncoding) { - MCE = getTarget().createCodeEmitter(*this, *Context); + const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); + MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, *Context); TAB = getTarget().createAsmBackend(getTargetTriple()); } @@ -159,7 +164,9 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, case CGFT_ObjectFile: { // Create the code emitter for the target if it exists. If not, .o file // emission fails. - MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); + const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); + MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, + *Context); TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; @@ -240,7 +247,8 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, // Create the code emitter for the target if it exists. If not, .o file // emission fails. - MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); + const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); + MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(),STI, *Ctx); TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index b1b86fe61e..86dc1083ce 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -11,19 +11,22 @@ #include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Triple.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> using namespace llvm; -void MCSubtargetInfo::InitMCSubtargetInfo(StringRef CPU, StringRef FS, - const SubtargetFeatureKV *PF, - const SubtargetFeatureKV *PD, - const SubtargetInfoKV *PI, - const InstrStage *IS, - const unsigned *OC, - const unsigned *FP, - unsigned NF, unsigned NP) { +void +MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, + const SubtargetFeatureKV *PF, + const SubtargetFeatureKV *PD, + const SubtargetInfoKV *PI, + const InstrStage *IS, + const unsigned *OC, + const unsigned *FP, + unsigned NF, unsigned NP) { + TargetTriple = TT; ProcFeatures = PF; ProcDesc = PD; ProcItins = PI; diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 8f77b04653..267ee52d3f 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -23,19 +23,21 @@ namespace llvm { +class ARMAsmPrinter; class ARMBaseTargetMachine; class FunctionPass; class JITCodeEmitter; -class formatted_raw_ostream; +class MachineInstr; class MCCodeEmitter; +class MCInst; +class MCInstrInfo; class MCObjectWriter; +class MCSubtargetInfo; class TargetAsmBackend; -class MachineInstr; -class ARMAsmPrinter; -class MCInst; +class formatted_raw_ostream; -MCCodeEmitter *createARMMCCodeEmitter(const Target &, - TargetMachine &TM, +MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx); TargetAsmBackend *createARMAsmBackend(const Target &, const std::string &); diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 4fcba11e5d..b92e02d047 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -21,8 +21,14 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/raw_ostream.h" + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + using namespace llvm; STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); @@ -32,19 +38,31 @@ namespace { class ARMMCCodeEmitter : public MCCodeEmitter { ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT - const TargetMachine &TM; - const TargetInstrInfo &TII; - const ARMSubtarget *Subtarget; + const MCInstrInfo &MCII; + const MCSubtargetInfo &STI; MCContext &Ctx; public: - ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) - : TM(tm), TII(*TM.getInstrInfo()), - Subtarget(&TM.getSubtarget<ARMSubtarget>()), Ctx(ctx) { + ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, + MCContext &ctx) + : MCII(mcii), STI(sti), Ctx(ctx) { } ~ARMMCCodeEmitter() {} + bool isThumb() const { + // FIXME: Can tablegen auto-generate this? + return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + } + bool isThumb2() const { + return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; + } + bool isTargetDarwin() const { + Triple TT(STI.getTargetTriple()); + Triple::OSType OS = TT.getOS(); + return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; + } + unsigned getMachineSoImmOpValue(unsigned SoImm) const; // getBinaryCodeForInstr - TableGen'erated function for getting the @@ -320,9 +338,10 @@ public: } // end anonymous namespace -MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM, +MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx) { - return new ARMMCCodeEmitter(TM, Ctx); + return new ARMMCCodeEmitter(MCII, STI, Ctx); } /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing @@ -330,7 +349,7 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM, /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const { - if (Subtarget->isThumb2()) { + if (isThumb2()) { // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are // set to 1111. @@ -349,7 +368,7 @@ unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned EncodedValue) const { - if (Subtarget->isThumb2()) { + if (isThumb2()) { EncodedValue &= 0xF0FFFFFF; EncodedValue |= 0x09000000; } @@ -362,7 +381,7 @@ unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, unsigned EncodedValue) const { - if (Subtarget->isThumb2()) { + if (isThumb2()) { EncodedValue &= 0x00FFFFFF; EncodedValue |= 0xEE000000; } @@ -374,7 +393,7 @@ unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, /// them to their Thumb2 form if we are currently in Thumb2 mode. unsigned ARMMCCodeEmitter:: VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { - if (Subtarget->isThumb2()) { + if (isThumb2()) { EncodedValue &= 0x0FFFFFFF; EncodedValue |= 0xE0000000; } @@ -515,7 +534,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const { // FIXME: This really, really shouldn't use TargetMachine. We don't want // coupling between MC and TM anywhere we can help it. - if (Subtarget->isThumb2()) + if (isThumb2()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); return getARMBranchTargetOpValue(MI, OpIdx, Fixups); @@ -624,7 +643,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, const MCExpr *Expr = MO.getExpr(); MCFixupKind Kind; - if (Subtarget->isThumb2()) + if (isThumb2()) Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); else Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); @@ -709,22 +728,22 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, switch (ARM16Expr->getKind()) { default: assert(0 && "Unsupported ARMFixup"); case ARMMCExpr::VK_ARM_HI16: - if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E)) - Kind = MCFixupKind(Subtarget->isThumb2() + if (!isTargetDarwin() && EvaluateAsPCRel(E)) + Kind = MCFixupKind(isThumb2() ? ARM::fixup_t2_movt_hi16_pcrel : ARM::fixup_arm_movt_hi16_pcrel); else - Kind = MCFixupKind(Subtarget->isThumb2() + Kind = MCFixupKind(isThumb2() ? ARM::fixup_t2_movt_hi16 : ARM::fixup_arm_movt_hi16); break; case ARMMCExpr::VK_ARM_LO16: - if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E)) - Kind = MCFixupKind(Subtarget->isThumb2() + if (!isTargetDarwin() && EvaluateAsPCRel(E)) + Kind = MCFixupKind(isThumb2() ? ARM::fixup_t2_movw_lo16_pcrel : ARM::fixup_arm_movw_lo16_pcrel); else - Kind = MCFixupKind(Subtarget->isThumb2() + Kind = MCFixupKind(isThumb2() ? ARM::fixup_t2_movw_lo16 : ARM::fixup_arm_movw_lo16); break; @@ -898,7 +917,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, assert(MO.isExpr() && "Unexpected machine operand type!"); const MCExpr *Expr = MO.getExpr(); MCFixupKind Kind; - if (Subtarget->isThumb2()) + if (isThumb2()) Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); else Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); @@ -1274,7 +1293,7 @@ void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { // Pseudo instructions don't get encoded. - const MCInstrDesc &Desc = TII.get(MI.getOpcode()); + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); uint64_t TSFlags = Desc.TSFlags; if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; @@ -1288,7 +1307,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); // Thumb 32-bit wide instructions need to emit the high order halfword // first. - if (Subtarget->isThumb() && Size == 4) { + if (isThumb() && Size == 4) { EmitConstant(Binary >> 16, 2, OS); EmitConstant(Binary & 0xffff, 2, OS); } else diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 1139cac394..83b63ab0c9 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -94,7 +94,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, } MCSubtargetInfo *X = new MCSubtargetInfo(); - InitARMMCSubtargetInfo(X, CPU, ArchFS); + InitARMMCSubtargetInfo(X, TT, CPU, ArchFS); return X; } diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index c105759ff7..6be75a1ea1 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -14,10 +14,11 @@ #include "Alpha.h" #include "AlphaInstrInfo.h" #include "AlphaMachineFunctionInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_MC_DESC @@ -381,3 +382,13 @@ unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const { AlphaFI->setGlobalRetAddr(GlobalRetAddr); return GlobalRetAddr; } + +MCInstrInfo *createAlphaMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitAlphaMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeAlphaMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo); +} diff --git a/lib/Target/Alpha/AlphaSubtarget.cpp b/lib/Target/Alpha/AlphaSubtarget.cpp index ccdc490d81..d559d7c549 100644 --- a/lib/Target/Alpha/AlphaSubtarget.cpp +++ b/lib/Target/Alpha/AlphaSubtarget.cpp @@ -40,7 +40,7 @@ AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU, MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitAlphaMCSubtargetInfo(X, CPU, FS); + InitAlphaMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/lib/Target/Blackfin/BlackfinInstrInfo.cpp index 0515a5f325..5870f7c9a4 100644 --- a/lib/Target/Blackfin/BlackfinInstrInfo.cpp +++ b/lib/Target/Blackfin/BlackfinInstrInfo.cpp @@ -14,10 +14,11 @@ #include "BlackfinInstrInfo.h" #include "BlackfinSubtarget.h" #include "Blackfin.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR @@ -254,3 +255,14 @@ loadRegFromAddr(MachineFunction &MF, SmallVectorImpl<MachineInstr*> &NewMIs) const { llvm_unreachable("loadRegFromAddr not implemented"); } + +MCInstrInfo *createBlackfinMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitBlackfinMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget, + createBlackfinMCInstrInfo); +} diff --git a/lib/Target/Blackfin/BlackfinSubtarget.cpp b/lib/Target/Blackfin/BlackfinSubtarget.cpp index 92914ae291..c7b50e4d53 100644 --- a/lib/Target/Blackfin/BlackfinSubtarget.cpp +++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp @@ -48,7 +48,7 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT, MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitBlackfinMCSubtargetInfo(X, CPU, FS); + InitBlackfinMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 54072b2f8d..e41e55716c 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -36,6 +36,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" @@ -61,6 +62,10 @@ extern "C" void LLVMInitializeCBackendTarget() { RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget); } +extern "C" void LLVMInitializeCBackendMCInstrInfo() { + RegisterMCInstrInfo<MCInstrInfo> X(TheCBackendTarget); +} + extern "C" void LLVMInitializeCBackendMCSubtargetInfo() { RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCBackendTarget); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 93b6d4c556..12fae9df87 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -17,10 +17,11 @@ #include "SPUTargetMachine.h" #include "SPUHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/MC/MCContext.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/MC/MCContext.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -450,3 +451,13 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) return true; } + +MCInstrInfo *createSPUMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSPUMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo); +} diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp index 3ce96b81a9..51fa1ea1b5 100644 --- a/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/lib/Target/CellSPU/SPUSubtarget.cpp @@ -70,7 +70,7 @@ bool SPUSubtarget::enablePostRAScheduler( MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSPUMCSubtargetInfo(X, CPU, FS); + InitSPUMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index c4280ef5a2..b1934370ce 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -22,7 +22,7 @@ #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/PassManager.h" -#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/CommandLine.h" @@ -76,6 +76,10 @@ extern "C" void LLVMInitializeCppBackendTarget() { RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget); } +extern "C" void LLVMInitializeCppBackendMCInstrInfo() { + RegisterMCInstrInfo<MCInstrInfo> X(TheCppBackendTarget); +} + extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() { RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCppBackendTarget); } diff --git a/lib/Target/MBlaze/MBlaze.h b/lib/Target/MBlaze/MBlaze.h index e9aff5b96b..26b869b143 100644 --- a/lib/Target/MBlaze/MBlaze.h +++ b/lib/Target/MBlaze/MBlaze.h @@ -22,13 +22,15 @@ namespace llvm { class FunctionPass; class MachineCodeEmitter; class MCCodeEmitter; + class MCInstrInfo; + class MCSubtargetInfo; class TargetAsmBackend; class formatted_raw_ostream; - MCCodeEmitter *createMBlazeMCCodeEmitter(const Target &, - TargetMachine &TM, + MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx); - + TargetAsmBackend *createMBlazeAsmBackend(const Target &, const std::string &); FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM); diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.cpp b/lib/Target/MBlaze/MBlazeInstrInfo.cpp index 0bd62ac529..8f7d956ccb 100644 --- a/lib/Target/MBlaze/MBlazeInstrInfo.cpp +++ b/lib/Target/MBlaze/MBlazeInstrInfo.cpp @@ -14,12 +14,13 @@ #include "MBlazeInstrInfo.h" #include "MBlazeTargetMachine.h" #include "MBlazeMachineFunction.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -294,3 +295,13 @@ unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { MBlazeFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } + +MCInstrInfo *createMBlazeMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMBlazeMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo); +} diff --git a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp index c573d4a28e..87f6caeb6c 100644 --- a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp +++ b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp @@ -29,13 +29,13 @@ namespace { class MBlazeMCCodeEmitter : public MCCodeEmitter { MBlazeMCCodeEmitter(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT void operator=(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT - const TargetMachine &TM; - const TargetInstrInfo &TII; + const MCInstrInfo &MCII; MCContext &Ctx; public: - MBlazeMCCodeEmitter(TargetMachine &tm, MCContext &ctx) - : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { + MBlazeMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, + MCContext &ctx) + : MCII(mcii), Ctx(ctx) { } ~MBlazeMCCodeEmitter() {} @@ -96,10 +96,10 @@ public: } // end anonymous namespace -MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const Target &, - TargetMachine &TM, +MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx) { - return new MBlazeMCCodeEmitter(TM, Ctx); + return new MBlazeMCCodeEmitter(MCII, STI, Ctx); } /// getMachineOpValue - Return binary encoding of operand. If the machine @@ -179,7 +179,7 @@ void MBlazeMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { unsigned Opcode = MI.getOpcode(); - const MCInstrDesc &Desc = TII.get(Opcode); + const MCInstrDesc &Desc = MCII.get(Opcode); uint64_t TSFlags = Desc.TSFlags; // Keep track of the current byte being emitted. unsigned CurByte = 0; diff --git a/lib/Target/MBlaze/MBlazeSubtarget.cpp b/lib/Target/MBlaze/MBlazeSubtarget.cpp index 54935b1ec5..54be1be37b 100644 --- a/lib/Target/MBlaze/MBlazeSubtarget.cpp +++ b/lib/Target/MBlaze/MBlazeSubtarget.cpp @@ -67,7 +67,7 @@ enablePostRAScheduler(CodeGenOpt::Level OptLevel, MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMBlazeMCSubtargetInfo(X, CPU, FS); + InitMBlazeMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 3738a98fd9..e9dfd5258a 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR @@ -334,3 +335,13 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 6; } + +MCInstrInfo *createMSP430MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMSP430MCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMSP430MCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo); +} diff --git a/lib/Target/MSP430/MSP430Subtarget.cpp b/lib/Target/MSP430/MSP430Subtarget.cpp index 6c5156f6d7..6509d5c2ff 100644 --- a/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/lib/Target/MSP430/MSP430Subtarget.cpp @@ -36,7 +36,7 @@ MSP430Subtarget::MSP430Subtarget(const std::string &TT, MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMSP430MCSubtargetInfo(X, CPU, FS); + InitMSP430MCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index b0a341fec1..3305a2ce32 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -15,10 +15,11 @@ #include "MipsTargetMachine.h" #include "MipsMachineFunction.h" #include "InstPrinter/MipsInstPrinter.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -459,3 +460,13 @@ unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { MipsFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } + +MCInstrInfo *createMipsMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMipsMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMipsMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo); +} diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index b2b26521ff..28e3c858e8 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -66,7 +66,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMipsMCSubtargetInfo(X, CPU, FS); + InitMipsMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/PTX/PTXInstrInfo.cpp b/lib/Target/PTX/PTXInstrInfo.cpp index 7f0fa8b23b..caa72b45ff 100644 --- a/lib/Target/PTX/PTXInstrInfo.cpp +++ b/lib/Target/PTX/PTXInstrInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -408,3 +409,14 @@ MachineBasicBlock *PTXInstrInfo::GetBranchTarget(const MachineInstr& inst) { assert(target.isMBB() && "FIXME: detect branch target operand"); return target.getMBB(); } + +MCInstrInfo *createPTXMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitPTXMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializePTXMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo); +} diff --git a/lib/Target/PTX/PTXSubtarget.cpp b/lib/Target/PTX/PTXSubtarget.cpp index a8a2ef7309..ff051672a3 100644 --- a/lib/Target/PTX/PTXSubtarget.cpp +++ b/lib/Target/PTX/PTXSubtarget.cpp @@ -71,7 +71,7 @@ std::string PTXSubtarget::getPTXVersionString() const { MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitPTXMCSubtargetInfo(X, CPU, FS); + InitPTXMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index 55852e69da..3c030a6835 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -31,6 +31,8 @@ namespace llvm { class MCInst; class MCCodeEmitter; class MCContext; + class MCInstrInfo; + class MCSubtargetInfo; class TargetMachine; class TargetAsmBackend; @@ -38,7 +40,8 @@ namespace llvm { FunctionPass *createPPCISelDag(PPCTargetMachine &TM); FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM, JITCodeEmitter &MCE); - MCCodeEmitter *createPPCMCCodeEmitter(const Target &, TargetMachine &TM, + MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx); TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &); diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 5b740b91a6..28d8f13bfc 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -12,21 +12,23 @@ //===----------------------------------------------------------------------===// #include "PPCInstrInfo.h" +#include "PPC.h" #include "PPCInstrBuilder.h" #include "PPCMachineFunctionInfo.h" #include "PPCPredicates.h" #include "PPCTargetMachine.h" #include "PPCHazardRecognizers.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/MC/MCAsmInfo.h" +#include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -652,3 +654,14 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 4; // PowerPC instructions are all 4 bytes } } + +MCInstrInfo *createPPCMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitPPCMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializePowerPCMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo); +} diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp index 65c2c82c51..250d545591 100644 --- a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -28,12 +28,12 @@ namespace { class PPCMCCodeEmitter : public MCCodeEmitter { PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT - const TargetMachine &TM; MCContext &Ctx; public: - PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx) - : TM(tm), Ctx(ctx) { + PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, + MCContext &ctx) + : Ctx(ctx) { } ~PPCMCCodeEmitter() {} @@ -79,9 +79,10 @@ public: } // end anonymous namespace -MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM, +MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, MCContext &Ctx) { - return new PPCMCCodeEmitter(TM, Ctx); + return new PPCMCCodeEmitter(MCII, STI, Ctx); } unsigned PPCMCCodeEmitter:: diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index bd40063d1c..8abc27a838 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -145,7 +145,7 @@ bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitPPCMCSubtargetInfo(X, CPU, FS); + InitPPCMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 17a41f2c9f..5738c1dd7f 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -12,14 +12,15 @@ //===----------------------------------------------------------------------===// #include "SparcInstrInfo.h" -#include "SparcSubtarget.h" #include "Sparc.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SmallVector.h" +#include "SparcMachineFunctionInfo.h" +#include "SparcSubtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" -#include "SparcMachineFunctionInfo.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -344,3 +345,13 @@ unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const SparcFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } + +MCInstrInfo *createSparcMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSparcMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeSparcMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); +} diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index 3513479814..31e20eb344 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -48,7 +48,7 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSparcMCSubtargetInfo(X, CPU, FS); + InitSparcMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index fae9a6a615..ae41d68d3e 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR @@ -437,3 +438,14 @@ SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); } } + +MCInstrInfo *createSystemZMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSystemZMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeSystemZMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, + createSystemZMCInstrInfo); +} diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp index f6707f9a20..fe3046b0cb 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -58,7 +58,7 @@ bool SystemZSubtarget::GVRequiresExtraLoad(const GlobalValue* GV, MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSystemZMCSubtargetInfo(X, CPU, FS); + InitSystemZMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index cdbbcd365f..c6f0b24129 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -64,7 +64,7 @@ private: /// or %es:(%edi) in 32bit mode. bool isDstOp(X86Operand &Op); - bool is64Bit() { + bool is64BitMode() const { // FIXME: Can tablegen auto-generate this? return (STI.getFeatureBits() & X86::Mode64Bit) != 0; } @@ -355,7 +355,7 @@ struct X86Operand : public MCParsedAsmOperand { } // end anonymous namespace. bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { - unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; + unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; return (Op.isMem() && (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && @@ -365,7 +365,7 @@ bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { } bool X86ATTAsmParser::isDstOp(X86Operand &Op) { - unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; + unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; return Op.isMem() && Op.Mem.SegReg == X86::ES && isa<MCConstantExpr>(Op.Mem.Disp) && @@ -396,7 +396,7 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo, // FIXME: This should be done using Requires<In32BitMode> and // Requires<In64BitMode> so "eiz" usage in 64-bit instructions // can be also checked. - if (RegNo == X86::RIZ && !is64Bit()) + if (RegNo == X86::RIZ && !is64BitMode()) return Error(Tok.getLoc(), "riz register in 64-bit mode only"); // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. @@ -816,7 +816,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" if (Name.startswith("movs") && Operands.size() == 3 && (Name == "movsb" || Name == "movsw" || Name == "movsl" || - (is64Bit() && Name == "movsq"))) { + (is64BitMode() && Name == "movsq"))) { X86Operand &Op = *(X86Operand*)Operands.begin()[1]; X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; if (isSrcOp(Op) && isDstOp(Op2)) { @@ -829,7 +829,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" if (Name.startswith("lods") && Operands.size() == 3 && (Name == "lods" || Name == "lodsb" || Name == "lodsw" || - Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { + Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) { X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); if (isSrcOp(*Op1) && Op2->isReg()) { @@ -859,7 +859,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" if (Name.startswith("stos") && Operands.size() == 3 && (Name == "stos" || Name == "stosb" || Name == "stosw" || - Name == "stosl" || (is64Bit() && Name == "stosq"))) { + Name == "stosl" || (is64BitMode() && Name == "stosq"))) { X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); if (isDstOp(*Op2) && Op1->isReg()) { diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index c34d3c92b7..04cb459a7f 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -127,7 +127,7 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, } MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X, CPUName, ArchFS); + InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); return X; } diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 1ffee86f92..ec52dfb3e7 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -23,10 +23,12 @@ namespace llvm { class FunctionPass; class JITCodeEmitter; +class MachineCodeEmitter; class MCCodeEmitter; class MCContext; +class MCInstrInfo; class MCObjectWriter; -class MachineCodeEmitter; +class MCSubtargetInfo; class Target; class TargetAsmBackend; class X86TargetMachine; @@ -58,10 +60,9 @@ FunctionPass *createSSEDomainFixPass(); FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, JITCodeEmitter &JCE); -MCCodeEmitter *createX86_32MCCodeEmitter(const Target &, TargetMachine &TM, - MCContext &Ctx); -MCCodeEmitter *createX86_64MCCodeEmitter(const Target &, TargetMachine &TM, - MCContext &Ctx); +MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, + MCContext &Ctx); TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &); TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &); diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index 04149e7348..c37a028297 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -18,26 +18,35 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Support/raw_ostream.h" + +#define GET_SUBTARGETINFO_ENUM +#include "X86GenSubtargetInfo.inc" + using namespace llvm; namespace { class X86MCCodeEmitter : public MCCodeEmitter { X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT - const TargetMachine &TM; - const TargetInstrInfo &TII; + const MCInstrInfo &MCII; + const MCSubtargetInfo &STI; MCContext &Ctx; - bool Is64BitMode; public: - X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit) - : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { - Is64BitMode = is64Bit; + X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, + MCContext &ctx) + : MCII(mcii), STI(sti), Ctx(ctx) { } ~X86MCCodeEmitter() {} + bool is64BitMode() const { + // FIXME: Can tablegen auto-generate this? + return (STI.getFeatureBits() & X86::Mode64Bit) != 0; + } + static unsigned GetX86RegNum(const MCOperand &MO) { return X86RegisterInfo::getX86RegNum(MO.getReg()); } @@ -126,16 +135,10 @@ public: } // end anonymous namespace -MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &, - TargetMachine &TM, - MCContext &Ctx) { - return new X86MCCodeEmitter(TM, Ctx, false); -} - -MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &, - TargetMachine &TM, - MCContext &Ctx) { - return new X86MCCodeEmitter(TM, Ctx, true); +MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, + MCContext &Ctx) { + return new X86MCCodeEmitter(MCII, STI, Ctx); } /// isDisp8 - Return true if this signed displacement fits in a 8-bit @@ -245,7 +248,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, // Handle %rip relative addressing. if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode - assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode"); + assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); @@ -284,7 +287,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, BaseRegNo != N86::ESP && // If there is no base register and we're in 64-bit mode, we need a SIB // byte to emit an addr that is just 'disp32' (the non-RIP relative form). - (!Is64BitMode || BaseReg != 0)) { + (!is64BitMode() || BaseReg != 0)) { if (BaseReg == 0) { // [disp32] in X86-32 mode EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); @@ -729,7 +732,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, // Emit the address size opcode prefix as needed. if ((TSFlags & X86II::AdSize) || - (MemOperand != -1 && Is64BitMode && Is32BitMemOperand(MI, MemOperand))) + (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand))) EmitByte(0x67, CurByte, OS); // Emit the operand size opcode prefix as needed. @@ -772,7 +775,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, // Handle REX prefix. // FIXME: Can this come before F2 etc to simplify emission? - if (Is64BitMode) { + if (is64BitMode()) { if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) EmitByte(0x40 | REX, CurByte, OS); } @@ -803,7 +806,7 @@ void X86MCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { unsigned Opcode = MI.getOpcode(); - const MCInstrDesc &Desc = TII.get(Opcode); + const MCInstrDesc &Desc = MCII.get(Opcode); uint64_t TSFlags = Desc.TSFlags; // Pseudo instructions don't get encoded. diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index e780615da3..d588934fc9 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -187,39 +187,53 @@ void X86Subtarget::AutoDetectSubtargetFeatures() { X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); - if ((EDX >> 15) & 1) HasCMov = true; - if ((EDX >> 23) & 1) X86SSELevel = MMX; - if ((EDX >> 25) & 1) X86SSELevel = SSE1; - if ((EDX >> 26) & 1) X86SSELevel = SSE2; - if (ECX & 0x1) X86SSELevel = SSE3; - if ((ECX >> 9) & 1) X86SSELevel = SSSE3; - if ((ECX >> 19) & 1) X86SSELevel = SSE41; - if ((ECX >> 20) & 1) X86SSELevel = SSE42; + if ((EDX >> 15) & 1) HasCMov = true; ToggleFeature(X86::FeatureCMOV); + if ((EDX >> 23) & 1) X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); + if ((EDX >> 25) & 1) X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); + if ((EDX >> 26) & 1) X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); + if (ECX & 0x1) X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); + if ((ECX >> 9) & 1) X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3); + if ((ECX >> 19) & 1) X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41); + if ((ECX >> 20) & 1) X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42); // FIXME: AVX codegen support is not ready. - //if ((ECX >> 28) & 1) { HasAVX = true; X86SSELevel = NoMMXSSE; } + //if ((ECX >> 28) & 1) { HasAVX = true; } ToggleFeature(X86::FeatureAVX); bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; - HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); - HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); - HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); - HasAES = IsIntel && ((ECX >> 25) & 0x1); + HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); ToggleFeature(X86::FeatureCLMUL); + HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); ToggleFeature(X86::FeatureFMA3); + HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT); + HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES); if (IsIntel || IsAMD) { // Determine if bit test memory instructions are slow. unsigned Family = 0; unsigned Model = 0; X86_MC::DetectFamilyModel(EAX, Family, Model); - IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13); + if (IsAMD || (Family == 6 && Model >= 13)) { + IsBTMemSlow = true; + ToggleFeature(X86::FeatureSlowBTMem); + } // If it's Nehalem, unaligned memory access is fast. - if (Family == 15 && Model == 26) + if (Family == 15 && Model == 26) { IsUAMemFast = true; + ToggleFeature(X86::FeatureFastUAMem); + } X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); - HasX86_64 = (EDX >> 29) & 0x1; - HasSSE4A = IsAMD && ((ECX >> 6) & 0x1); - HasFMA4 = IsAMD && ((ECX >> 16) & 0x1); + if ((EDX >> 29) & 0x1) { + HasX86_64 = true; + ToggleFeature(X86::Feature64Bit); + } + if (IsAMD && ((ECX >> 6) & 0x1)) { + HasSSE4A = true; + ToggleFeature(X86::FeatureSSE4A); + } + if (IsAMD && ((ECX >> 16) & 0x1)) { + HasFMA4 = true; + ToggleFeature(X86::FeatureFMA4); + } } } @@ -270,22 +284,30 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, // If feature string is not empty, parse features string. ParseSubtargetFeatures(CPUName, FullFS); - - if (HasAVX) - X86SSELevel = NoMMXSSE; } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); // Make sure 64-bit features are available in 64-bit mode. if (In64BitMode) { - HasX86_64 = true; - HasCMov = true; + HasX86_64 = true; ToggleFeature(X86::Feature64Bit); + HasCMov = true; ToggleFeature(X86::FeatureCMOV); - if (!HasAVX && X86SSELevel < SSE2) + if (!HasAVX && X86SSELevel < SSE2) { X86SSELevel = SSE2; + ToggleFeature(X86::FeatureSSE1); + ToggleFeature(X86::FeatureSSE2); + } } } + + // It's important to keep the MCSubtargetInfo feature bits in sync with + // target data structure which is shared with MC code emitter, etc. + if (In64BitMode) + ToggleFeature(X86::Mode64Bit); + + if (HasAVX) + X86SSELevel = NoMMXSSE; DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 016111cadd..2b1da45201 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -68,9 +68,9 @@ extern "C" void LLVMInitializeX86Target() { // Register the code emitter. TargetRegistry::RegisterCodeEmitter(TheX86_32Target, - createX86_32MCCodeEmitter); + createX86MCCodeEmitter); TargetRegistry::RegisterCodeEmitter(TheX86_64Target, - createX86_64MCCodeEmitter); + createX86MCCodeEmitter); // Register the asm backend. TargetRegistry::RegisterAsmBackend(TheX86_32Target, diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index c39571d3e4..693a2fe7a5 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -396,3 +397,13 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); return false; } + +MCInstrInfo *createXCoreMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitXCoreMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeXCoreMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); +} diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp index 8ede9366fc..5181364070 100644 --- a/lib/Target/XCore/XCoreSubtarget.cpp +++ b/lib/Target/XCore/XCoreSubtarget.cpp @@ -33,7 +33,7 @@ XCoreSubtarget::XCoreSubtarget(const std::string &TT, MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitXCoreMCSubtargetInfo(X, CPU, FS); + InitXCoreMCSubtargetInfo(X, TT, CPU, FS); return X; } diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s index 1fad8f13b6..4cc986a3e1 100644 --- a/test/MC/ARM/mode-switch.s +++ b/test/MC/ARM/mode-switch.s @@ -1,9 +1,10 @@ @ Test ARM / Thumb mode switching with .code @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s .code 16 -@ CHECK: add.w r0, r0, r1 @ encoding: [0x01,0x00,0x00,0xeb] +@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] add.w r0, r0, r1 .code 32 diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index 6d5b09c557..8e12b91124 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -201,6 +201,7 @@ int main(int argc, char **argv) { // Initialize targets first, so that --version shows registered targets. InitializeAllTargets(); + InitializeAllMCInstrInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp index d73f7e5cf7..c98641a33a 100644 --- a/tools/llvm-mc/llvm-mc.cpp +++ b/tools/llvm-mc/llvm-mc.cpp @@ -17,6 +17,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -341,6 +342,7 @@ static int AssembleInput(const char *ProgName) { TM->getTargetLowering()->getObjFileLowering(); const_cast<TargetLoweringObjectFile&>(TLOF).Initialize(Ctx, *TM); + OwningPtr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); OwningPtr<MCSubtargetInfo> STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); @@ -351,7 +353,7 @@ static int AssembleInput(const char *ProgName) { MCCodeEmitter *CE = 0; TargetAsmBackend *TAB = 0; if (ShowEncoding) { - CE = TheTarget->createCodeEmitter(*TM, Ctx); + CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); TAB = TheTarget->createAsmBackend(TripleName); } Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true, @@ -362,7 +364,7 @@ static int AssembleInput(const char *ProgName) { Str.reset(createNullStreamer(Ctx)); } else { assert(FileType == OFT_ObjectFile && "Invalid file type!"); - MCCodeEmitter *CE = TheTarget->createCodeEmitter(*TM, Ctx); + MCCodeEmitter *CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); TargetAsmBackend *TAB = TheTarget->createAsmBackend(TripleName); Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *TAB, FOS, CE, RelaxAll, @@ -451,6 +453,7 @@ int main(int argc, char **argv) { llvm::InitializeAllTargetInfos(); // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); + llvm::InitializeAllMCInstrInfos(); llvm::InitializeAllMCSubtargetInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index e87b22e98e..4813b42c62 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -666,8 +666,9 @@ void SubtargetEmitter::run(raw_ostream &OS) { // MCInstrInfo initialization routine. OS << "static inline void Init" << Target - << "MCSubtargetInfo(MCSubtargetInfo *II, StringRef CPU, StringRef FS) {\n"; - OS << " II->InitMCSubtargetInfo(CPU, FS, "; + << "MCSubtargetInfo(MCSubtargetInfo *II, " + << "StringRef TT, StringRef CPU, StringRef FS) {\n"; + OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; else @@ -719,7 +720,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " << "StringRef FS)\n" << " : TargetSubtargetInfo() {\n" - << " InitMCSubtargetInfo(CPU, FS, "; + << " InitMCSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; else |