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-rw-r--r--include/llvm/CodeGen/RegisterPressure.h7
-rw-r--r--lib/CodeGen/MachineScheduler.cpp4
-rw-r--r--lib/CodeGen/RegisterPressure.cpp26
-rw-r--r--lib/CodeGen/ScheduleDAGInstrs.cpp14
-rw-r--r--test/CodeGen/X86/2012-11-30-regpres-dbg.ll43
5 files changed, 74 insertions, 20 deletions
diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h
index 30326d05df..cc9b1c4643 100644
--- a/include/llvm/CodeGen/RegisterPressure.h
+++ b/include/llvm/CodeGen/RegisterPressure.h
@@ -150,7 +150,8 @@ class RegPressureTracker {
bool RequireIntervals;
/// Register pressure corresponds to liveness before this instruction
- /// iterator. It may point to the end of the block rather than an instruction.
+ /// iterator. It may point to the end of the block or a DebugValue rather than
+ /// an instruction.
MachineBasicBlock::const_iterator CurrPos;
/// Pressure map indexed by pressure set ID, not class ID.
@@ -184,6 +185,10 @@ public:
// position changes while pressure does not.
void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
+ /// \brief Get the SlotIndex for the first nondebug instruction including or
+ /// after the current position.
+ SlotIndex getCurrSlot() const;
+
/// Recede across the previous instruction.
bool recede();
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index cc7aabda3c..0789a740d5 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -603,7 +603,11 @@ void ScheduleDAGMI::initQueues() {
SchedImpl->registerRoots();
+ // Advance past initial DebugValues.
+ assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
+ TopRPTracker.setPos(CurrentTop);
+
CurrentBottom = RegionEnd;
}
diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp
index 543c426458..c7763dc55f 100644
--- a/lib/CodeGen/RegisterPressure.cpp
+++ b/lib/CodeGen/RegisterPressure.cpp
@@ -181,9 +181,6 @@ void RegPressureTracker::init(const MachineFunction *mf,
}
CurrPos = pos;
- while (CurrPos != MBB->end() && CurrPos->isDebugValue())
- ++CurrPos;
-
CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);
if (RequireIntervals)
@@ -214,11 +211,20 @@ bool RegPressureTracker::isBottomClosed() const {
MachineBasicBlock::const_iterator());
}
+
+SlotIndex RegPressureTracker::getCurrSlot() const {
+ MachineBasicBlock::const_iterator IdxPos = CurrPos;
+ while (IdxPos != MBB->end() && IdxPos->isDebugValue())
+ ++IdxPos;
+ if (IdxPos == MBB->end())
+ return LIS->getMBBEndIdx(MBB);
+ return LIS->getInstructionIndex(IdxPos).getRegSlot();
+}
+
/// Set the boundary for the top of the region and summarize live ins.
void RegPressureTracker::closeTop() {
if (RequireIntervals)
- static_cast<IntervalPressure&>(P).TopIdx =
- LIS->getInstructionIndex(CurrPos).getRegSlot();
+ static_cast<IntervalPressure&>(P).TopIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).TopPos = CurrPos;
@@ -236,11 +242,7 @@ void RegPressureTracker::closeTop() {
/// Set the boundary for the bottom of the region and summarize live outs.
void RegPressureTracker::closeBottom() {
if (RequireIntervals)
- if (CurrPos == MBB->end())
- static_cast<IntervalPressure&>(P).BottomIdx = LIS->getMBBEndIdx(MBB);
- else
- static_cast<IntervalPressure&>(P).BottomIdx =
- LIS->getInstructionIndex(CurrPos).getRegSlot();
+ static_cast<IntervalPressure&>(P).BottomIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).BottomPos = CurrPos;
@@ -510,7 +512,7 @@ bool RegPressureTracker::advance() {
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = getCurrSlot();
// Open the bottom of the region using slot indexes.
if (isBottomClosed()) {
@@ -769,7 +771,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
const LiveInterval *LI = &LIS->getInterval(Reg);
// FIXME: allow the caller to pass in the list of vreg uses that remain to
// be bottom-scheduled to avoid searching uses at each query.
- SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIndex CurrIdx = getCurrSlot();
if (LI->killedAt(SlotIdx)
&& !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {
decreaseVirtRegPressure(Reg);
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index fd75576c78..2a41293892 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -713,17 +713,17 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
addSchedBarrierDeps();
// Walk the list of instructions, from bottom moving up.
- MachineInstr *PrevMI = NULL;
+ MachineInstr *DbgMI = NULL;
for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
- if (MI && PrevMI) {
- DbgValues.push_back(std::make_pair(PrevMI, MI));
- PrevMI = NULL;
+ if (MI && DbgMI) {
+ DbgValues.push_back(std::make_pair(DbgMI, MI));
+ DbgMI = NULL;
}
if (MI->isDebugValue()) {
- PrevMI = MI;
+ DbgMI = MI;
continue;
}
if (RPTracker) {
@@ -917,8 +917,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
}
}
}
- if (PrevMI)
- FirstDbgValue = PrevMI;
+ if (DbgMI)
+ FirstDbgValue = DbgMI;
Defs.clear();
Uses.clear();
diff --git a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
new file mode 100644
index 0000000000..d290d514cc
--- /dev/null
+++ b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-misched \
+; RUN: -verify-machineinstrs | FileCheck %s
+;
+; Test RegisterPressure handling of DBG_VALUE.
+;
+; CHECK: %entry
+; CHECK: DEBUG_VALUE: callback
+; CHECK: ret
+
+%struct.btCompoundLeafCallback = type { i32, i32 }
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+define void @test() unnamed_addr uwtable ssp align 2 {
+entry:
+ %callback = alloca %struct.btCompoundLeafCallback, align 8
+ br i1 undef, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ unreachable
+
+if.end: ; preds = %entry
+ call void @llvm.dbg.declare(metadata !{%struct.btCompoundLeafCallback* %callback}, metadata !3)
+ %m = getelementptr inbounds %struct.btCompoundLeafCallback* %callback, i64 0, i32 1
+ store i32 0, i32* undef, align 8
+ %cmp12447 = icmp sgt i32 undef, 0
+ br i1 %cmp12447, label %for.body.lr.ph, label %invoke.cont44
+
+for.body.lr.ph: ; preds = %if.end
+ unreachable
+
+invoke.cont44: ; preds = %if.end
+ ret void
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet", metadata !"clang version 3.3 (trunk 168984) (llvm/trunk 168983)", i1 true, i1 true, metadata !"", i32 0, metadata !1, null, null, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Bullet/MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !2}
+!2 = metadata !{null, null}
+!3 = metadata !{i32 786688, null, metadata !"callback", null, i32 214, metadata !4, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [callback] [line 214]
+!4 = metadata !{i32 786451, null, metadata !"btCompoundLeafCallback", metadata !5, i32 90, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [from ]
+!5 = metadata !{i32 786473, metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet", null} ; [ DW_TAG_file_type ]
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 04:07:53 +0000