diff options
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/f16c-intrinsics.ll | 14 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 72a18e7d79..c49777516d 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -8304,6 +8304,12 @@ let Predicates = [HasF16C] in { defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L; defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>; defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L; + + // Pattern match vcvtph2ps of a scalar i64 load. + def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)), + (VCVTPH2PSrm addr:$src)>; + def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)), + (VCVTPH2PSrm addr:$src)>; } //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/X86/f16c-intrinsics.ll b/test/CodeGen/X86/f16c-intrinsics.ll index 2135f9409c..514d929f44 100644 --- a/test/CodeGen/X86/f16c-intrinsics.ll +++ b/test/CodeGen/X86/f16c-intrinsics.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+avx,+f16c | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+avx,+f16c | FileCheck %s define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) { ; CHECK: vcvtph2ps @@ -30,3 +31,16 @@ define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) { ret <8 x i16> %res } declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly + +define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) { +; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar +; CHECK-NOT: vmov +; CHECK: vcvtph2ps (% + + %load = load i64* %ptr + %ins1 = insertelement <2 x i64> undef, i64 %load, i32 0 + %ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1 + %bc = bitcast <2 x i64> %ins2 to <8 x i16> + %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) #2 + ret <4 x float> %res +} |