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path: root/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp252
1 files changed, 126 insertions, 126 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 9ec084663f..a10d167579 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -118,13 +118,13 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
NewVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
Op0, DAG.getValueType(NewVT),
@@ -150,7 +150,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
SDValue Op = N->getOperand(1);
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType() != EltVT)
// FIXME: Can this happen for floating point types?
Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
@@ -177,7 +177,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
- MVT DestVT = N->getValueType(0).getVectorElementType();
+ EVT DestVT = N->getValueType(0).getVectorElementType();
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
}
@@ -185,7 +185,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
// If the operand is wider than the vector element type then it is implicitly
// truncated. Make that explicit here.
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
SDValue InOp = N->getOperand(0);
if (InOp.getValueType() != EltVT)
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
@@ -213,7 +213,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
+ return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
@@ -232,8 +232,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
- MVT NVT = N->getValueType(0).getVectorElementType();
- MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
+ EVT NVT = N->getValueType(0).getVectorElementType();
+ EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
@@ -247,16 +247,16 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
- DAG.getValueType(MVT::i1));
+ DAG.getValueType(EVT::i1));
// Truncate to the final type.
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
}
// The SETCC result type is smaller than the vector element type.
- // If the SetCC result is not sign-extended, chop it down to MVT::i1.
+ // If the SetCC result is not sign-extended, chop it down to EVT::i1.
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
- Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
+ Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
}
@@ -472,12 +472,12 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
DebugLoc dl = N->getDebugLoc();
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
switch (getTypeAction(InVT)) {
@@ -512,8 +512,8 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
}
// In the general case, convert the input to an integer and split it by hand.
- MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
- MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
+ EVT LoIntVT = EVT::getIntegerVT(LoVT.getSizeInBits());
+ EVT HiIntVT = EVT::getIntegerVT(HiVT.getSizeInBits());
if (TLI.isBigEndian())
std::swap(LoIntVT, HiIntVT);
@@ -527,7 +527,7 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
@@ -549,7 +549,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
return;
}
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
@@ -561,7 +561,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@@ -574,11 +574,11 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
// Split the input.
SDValue VLo, VHi;
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -594,7 +594,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -617,10 +617,10 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT IdxVT = Idx.getValueType();
+ EVT IdxVT = Idx.getValueType();
DebugLoc dl = N->getDebugLoc();
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
@@ -658,8 +658,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
}
// Spill the vector to the stack.
- MVT VecVT = Vec.getValueType();
- MVT EltVT = VecVT.getVectorElementType();
+ EVT VecVT = Vec.getValueType();
+ EVT EltVT = VecVT.getVectorElementType();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
@@ -667,7 +667,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
// so use a truncating store.
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT());
Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
// Load the Lo part from the stack slot.
@@ -685,7 +685,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
@@ -695,7 +695,7 @@ void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = LD->getDebugLoc();
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
@@ -705,11 +705,11 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
- MVT MemoryVT = LD->getMemoryVT();
+ EVT MemoryVT = LD->getMemoryVT();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
@@ -725,7 +725,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Legalized the chain result - switch anything that used the old chain to
@@ -734,14 +734,14 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
}
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc DL = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
SDValue LL, LH, RL, RH;
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -760,16 +760,16 @@ void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Get the dest types - they may not match the input types, e.g. int_to_fp.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -785,7 +785,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -806,7 +806,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
- MVT NewVT = Inputs[0].getValueType();
+ EVT NewVT = Inputs[0].getValueType();
unsigned NewElts = NewVT.getVectorNumElements();
// If Lo or Hi uses elements from at most two of the four input vectors, then
@@ -864,7 +864,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
}
if (useBuildVector) {
- MVT EltVT = NewVT.getVectorElementType();
+ EVT EltVT = NewVT.getVectorElementType();
SmallVector<SDValue, 16> SVOps;
// Extract the input elements by hand.
@@ -969,13 +969,13 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
// The result has a legal vector type, but the input needs splitting.
- MVT ResVT = N->getValueType(0);
+ EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Lo, Hi);
- MVT InVT = Lo.getValueType();
+ EVT InVT = Lo.getValueType();
- MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
+ EVT OutVT = EVT::getVectorVT(ResVT.getVectorElementType(),
InVT.getVectorNumElements());
Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
@@ -1003,7 +1003,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
- MVT SubVT = N->getValueType(0);
+ EVT SubVT = N->getValueType(0);
SDValue Idx = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
SDValue Lo, Hi;
@@ -1025,7 +1025,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT VecVT = Vec.getValueType();
+ EVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
@@ -1044,7 +1044,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
}
// Store the vector to the stack.
- MVT EltVT = VecVT.getVectorElementType();
+ EVT EltVT = VecVT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
@@ -1066,13 +1066,13 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
- MVT MemoryVT = N->getMemoryVT();
+ EVT MemoryVT = N->getMemoryVT();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
@@ -1097,7 +1097,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
@@ -1197,7 +1197,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
// Binary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp1 = GetWidenedVector(N->getOperand(0));
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
@@ -1207,12 +1207,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
SDValue InOp = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
unsigned Opcode = N->getOpcode();
unsigned InVTNumElts = InVT.getVectorNumElements();
@@ -1254,7 +1254,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
unsigned i;
for (i=0; i < MinElts; ++i)
@@ -1270,16 +1270,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
SDValue ShOp = N->getOperand(1);
- MVT ShVT = ShOp.getValueType();
+ EVT ShVT = ShOp.getValueType();
if (getTypeAction(ShVT) == WidenVector) {
ShOp = GetWidenedVector(ShOp);
ShVT = ShOp.getValueType();
}
- MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
+ EVT ShWidenVT = EVT::getVectorVT(ShVT.getVectorElementType(),
WidenVT.getVectorNumElements());
if (ShVT != ShWidenVT)
ShOp = ModifyToType(ShOp, ShWidenVT);
@@ -1289,16 +1289,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
// Unary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
}
SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT InVT = InOp.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(InVT)) {
@@ -1338,13 +1338,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
// Determine new input vector type. The new input vector type will use
// the same element type (if its a vector) or use the input type as a
// vector. It is the same size as the type to widen to.
- MVT NewInVT;
+ EVT NewInVT;
unsigned NewNumElts = WidenSize / InSize;
if (InVT.isVector()) {
- MVT InEltVT = InVT.getVectorElementType();
- NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
+ EVT InEltVT = InVT.getVectorElementType();
+ NewInVT= EVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
} else {
- NewInVT = MVT::getVectorVT(InVT, NewNumElts);
+ NewInVT = EVT::getVectorVT(InVT, NewNumElts);
}
if (TLI.isTypeLegal(NewInVT)) {
@@ -1376,11 +1376,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
// Build a vector with undefined for the new nodes.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
unsigned NumElts = VT.getVectorNumElements();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
@@ -1392,8 +1392,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
- MVT InVT = N->getOperand(0).getValueType();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT InVT = N->getOperand(0).getValueType();
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
unsigned NumOperands = N->getNumOperands();
@@ -1442,7 +1442,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
}
// Fall back to use extracts and build vector.
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned NumInElts = InVT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(WidenNumElts);
unsigned Idx = 0;
@@ -1466,12 +1466,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
SDValue RndOp = N->getOperand(3);
SDValue SatOp = N->getOperand(4);
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
SDValue DTyOp = DAG.getValueType(WidenVT);
SDValue STyOp = DAG.getValueType(InWidenVT);
@@ -1518,7 +1518,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
DTyOp = DAG.getValueType(EltVT);
STyOp = DAG.getValueType(InEltVT);
@@ -1539,8 +1539,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
SDValue Idx = N->getOperand(1);
@@ -1549,7 +1549,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
@@ -1567,8 +1567,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
// We could try widening the input to the right length but for now, extract
// the original elements, fill the rest with undefs and build a vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = VT.getVectorElementType();
- MVT IdxVT = Idx.getValueType();
+ EVT EltVT = VT.getVectorElementType();
+ EVT IdxVT = Idx.getValueType();
unsigned NumElts = VT.getVectorNumElements();
unsigned i;
if (CIdx) {
@@ -1600,8 +1600,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
- MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
- MVT LdVT = LD->getMemoryVT();
+ EVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT LdVT = LD->getMemoryVT();
DebugLoc dl = N->getDebugLoc();
assert(LdVT.isVector() && WidenVT.isVector());
@@ -1620,8 +1620,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
// For extension loads, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the load and build a vector.
- MVT EltVT = WidenVT.getVectorElementType();
- MVT LdEltVT = LdVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
+ EVT LdEltVT = LdVT.getVectorElementType();
unsigned NumElts = LdVT.getVectorNumElements();
// Load each element and widen
@@ -1660,7 +1660,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
if (LdChain.size() == 1)
NewChain = LdChain[0];
else
- NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
LdChain.size());
// Modified the chain - switch anything that used the old chain to use
@@ -1671,20 +1671,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
WidenVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue Cond1 = N->getOperand(0);
- MVT CondVT = Cond1.getValueType();
+ EVT CondVT = Cond1.getValueType();
if (CondVT.isVector()) {
- MVT CondEltVT = CondVT.getVectorElementType();
- MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
+ EVT CondEltVT = CondVT.getVectorElementType();
+ EVT CondWidenVT = EVT::getVectorVT(CondEltVT, WidenNumElts);
if (getTypeAction(CondVT) == WidenVector)
Cond1 = GetWidenedVector(Cond1);
@@ -1708,15 +1708,15 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getUNDEF(WidenVT);
}
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned NumElts = VT.getVectorNumElements();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
@@ -1738,13 +1738,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp1 = N->getOperand(0);
- MVT InVT = InOp1.getValueType();
+ EVT InVT = InOp1.getValueType();
assert(InVT.isVector() && "can not widen non vector type");
- MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
+ EVT WidenInVT = EVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
InOp1 = GetWidenedVector(InOp1);
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
@@ -1812,15 +1812,15 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
// Since the result is legal and the input is illegal, it is unlikely
// that we can fix the input to a legal type so unroll the convert
// into some scalar code and create a nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
unsigned Opcode = N->getOpcode();
SmallVector<SDValue, 16> Ops(NumElts);
@@ -1833,9 +1833,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
}
SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InWidenVT = InOp.getValueType();
+ EVT InWidenVT = InOp.getValueType();
DebugLoc dl = N->getDebugLoc();
// Check if we can convert between two legal vector types and extract.
@@ -1843,7 +1843,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
unsigned Size = VT.getSizeInBits();
if (InWidenSize % Size == 0 && !VT.isVector()) {
unsigned NewNumElts = InWidenSize / Size;
- MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
+ EVT NewVT = EVT::getVectorVT(VT, NewNumElts);
if (TLI.isTypeLegal(NewVT)) {
SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
@@ -1858,13 +1858,13 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
// If the input vector is not legal, it is likely that we will not find a
// legal vector of the same size. Replace the concatenate vector with a
// nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(NumElts);
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
unsigned NumInElts = InVT.getVectorNumElements();
unsigned Idx = 0;
@@ -1899,8 +1899,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
SDValue ValOp = GetWidenedVector(ST->getValue());
DebugLoc dl = N->getDebugLoc();
- MVT StVT = ST->getMemoryVT();
- MVT ValVT = ValOp.getValueType();
+ EVT StVT = ST->getMemoryVT();
+ EVT ValVT = ValOp.getValueType();
// It must be true that we the widen vector type is bigger than where
// we need to store.
assert(StVT.isVector() && ValOp.getValueType().isVector());
@@ -1911,8 +1911,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
// For truncating stores, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the store.
- MVT StEltVT = StVT.getVectorElementType();
- MVT ValEltVT = ValVT.getVectorElementType();
+ EVT StEltVT = StVT.getVectorElementType();
+ EVT ValEltVT = ValVT.getVectorElementType();
unsigned Increment = ValEltVT.getSizeInBits() / 8;
unsigned NumElts = StVT.getVectorNumElements();
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
@@ -1941,7 +1941,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
- MVT::Other,&StChain[0],StChain.size());
+ EVT::Other,&StChain[0],StChain.size());
}
//===----------------------------------------------------------------------===//
@@ -1958,8 +1958,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
// Returns NewVecVT and NewEltVT - the vector type and its associated
// element type.
static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
- MVT VecVT,
- MVT& NewEltVT, MVT& NewVecVT) {
+ EVT VecVT,
+ EVT& NewEltVT, EVT& NewVecVT) {
unsigned EltWidth = Width + 1;
if (TLI.isTypeLegal(VecVT)) {
// We start with the preferred with, making it a power of 2 and find a
@@ -1969,9 +1969,9 @@ static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewVecVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
} else {
@@ -1984,9 +1984,9 @@ static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewEltVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
}
@@ -2000,7 +2000,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
unsigned Alignment,
bool isVolatile,
unsigned LdWidth,
- MVT ResType,
+ EVT ResType,
DebugLoc dl) {
// The strategy assumes that we can efficiently load powers of two widths.
// The routines chops the vector into the largest power of 2 load and
@@ -2011,7 +2011,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
// the load is nonvolatile, we an use a wider load for the value.
// Find the vector type that can load from.
- MVT NewEltVT, NewVecVT;
+ EVT NewEltVT, NewVecVT;
unsigned NewEltVTWidth;
FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2075,8 +2075,8 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
// want to store. This avoids requiring a stack convert.
// Find a width of the element type we can store with
- MVT WidenVT = ValOp.getValueType();
- MVT NewEltVT, NewVecVT;
+ EVT WidenVT = ValOp.getValueType();
+ EVT NewEltVT, NewVecVT;
FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2125,10 +2125,10 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
/// input vector must have the same element type as NVT.
-SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
+SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
// Note that InOp might have been widened so it might already have
// the right width or it might need be narrowed.
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");
DebugLoc dl = InOp.getDebugLoc();
@@ -2156,7 +2156,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
// Fall back to extract and build.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = NVT.getVectorElementType();
+ EVT EltVT = NVT.getVectorElementType();
unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
unsigned Idx;
for (Idx = 0; Idx < MinNumElts; ++Idx)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 03:06:47 +0000